Sigang Ryu

Orcid: 0000-0001-5307-8117

According to our database1, Sigang Ryu authored at least 9 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2021
A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2019
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery.
IEEE J. Solid State Circuits, 2019

2016
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function.
IEEE J. Solid State Circuits, 2014

2012
A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012


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