E-Hung Chen

According to our database1, E-Hung Chen authored at least 10 papers between 2008 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

2014
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm.
IEEE J. Solid State Circuits, 2013

A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Power Optimized ADC-Based Serial Link Receiver.
IEEE J. Solid State Circuits, 2012

A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010
ADC-Based Serial I/O Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2008
Edge and Data Adaptive Equalization of Serial-Link Transceivers.
IEEE J. Solid State Circuits, 2008

Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric.
IEEE J. Solid State Circuits, 2008


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