Haruo Shimamoto

According to our database, Haruo Shimamoto authored at least 14 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Analysis and evaluation of noise coupling between through-silicon-vias.

Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi

IEICE Electron. Express, 2021

Landside capacitor efficacy among multi-chip-module using Si-interposer.

Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi

IEICE Electron. Express, 2021

2020

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices.

Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi

IEEE J. Solid State Circuits, 2020

2019

Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs.

Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core.

Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2017

Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits.

Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi

Microelectron. Reliab., 2017

2016

Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits.

Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi

Microelectron. Reliab., 2016

Validation of TSV thermo-mechanical simulation by stress measurement.

Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi

Microelectron. Reliab., 2016

Fabrication and stress analysis of annular-trench-isolated TSV.

Wei Feng, Tung Thanh Bui, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi

Microelectron. Reliab., 2016

Wet cleaning process for high-yield via-last TSV formation.

Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2014

Analysis of thermal stress distribution for TSV with novel structure.

Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2011

Development of high accuracy wafer thinning and pickup technology for thin wafer.

Kosuke Kitaichi, Haruo Shimamoto, Chuichi Miyazaki, Yoshiyuki Abe, Sigeaki Saito, Shoji Yasunaga

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

Development of high accuracy wafer thinning and pickup technology for thin wafer.

Chuichi Miyazaki, Haruo Shimamoto, Toshihide Uematsu, Yoshiyuki Abe, Kosuke Kitaichi, Tadahiro Morifuji, Shoji Yasunaga

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Development of wafer thinning and dicing technology for thin wafer.

Chuichi Miyazaki, Haruo Shimamoto, Toshihide Uematsu, Yoshiyuki Abe

Proceedings of the IEEE International Conference on 3D System Integration, 2009