Yuuki Araga

Orcid: 0000-0002-2081-3303

According to our database1, Yuuki Araga authored at least 14 papers between 2010 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Analysis and evaluation of noise coupling between through-silicon-vias.
IEICE Electron. Express, 2021

Landside capacitor efficacy among multi-chip-module using Si-interposer.
IEICE Electron. Express, 2021

2020
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices.
IEEE J. Solid State Circuits, 2020

2019
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
A study on substrate noise coupling among TSVs in 3D chip stack.
IEICE Electron. Express, 2018

2015
Guard-ring monitoring system for inspecting defects in TSV-based data buses.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Substrate monitoring system for inspecting defects in TSV-based data buses.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Noise analysis using on-chip waveform monitor in bandgap voltage references.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

2011
A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength.
IEICE Trans. Electron., 2011

A diagnosis testbench of analog IP cores against on-chip environmental disturbances.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

In-tier diagnosis of power domains in 3D TSV ICs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
An on-chip waveform capturing technique pursuing minimum cost of integration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010


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