Hector Villacorta

Orcid: 0000-0003-4405-4935

According to our database1, Hector Villacorta authored at least 16 papers between 2010 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

2021
Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell.
J. Electron. Test., 2021

2020
Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells.
Proceedings of the IEEE Latin-American Test Symposium, 2020

2019
Modeling and Detectability of Full Open Gate Defects in FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2018
TCAD analysis and modeling for NBTI mechanism in FinFET transistors.
IEICE Electron. Express, 2018

An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

2016
Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability.
J. Electron. Test., 2016

Behavior and test of open-gate defects in FinFET based cells.
Proceedings of the 21th IEEE European Test Symposium, 2016

2015
Low V<sub>DD</sub> and body bias conditions for testing bridge defects in the presence of process variations.
Microelectron. J., 2015

Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell.
Proceedings of the 16th Latin-American Test Symposium, 2015

2014
Skew violation verification in digital interconnect signals based on signal addition.
IEICE Electron. Express, 2014

Analysis of fin height on FinFET SRAM cell hardening.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths.
IEEE Des. Test, 2013

Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias.
Proceedings of the 14th Latin American Test Workshop, 2013

2012
Resistive bridge defect detection enhancement under parameter variations combining Low V<sub>DD</sub> and body bias in a delay based test.
Microelectron. Reliab., 2012

2010
Reliability analysis of small delay defects in vias located in signal paths.
Proceedings of the 11th Latin American Test Workshop, 2010


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