Heng Zhang

Affiliations:
  • Broadcom, Irvine, CA, USA
  • Texas A&M University, College Station, TX, USA (PhD 2010)


According to our database1, Heng Zhang authored at least 10 papers between 2013 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

Online presence:

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Bibliography

2025

2024
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022
An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2017
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.
IEEE J. Solid State Circuits, 2015

2014
A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS.
IEEE J. Solid State Circuits, 2014

2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013


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