Hiromi Notani

According to our database, Hiromi Notani authored at least 8 papers between 1991 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

Delayed-ABC SOI for crosstalk noise repair.

Akira Tada, Hiromi Notani, Genichi Tanaka, Toshiaki Iwamatsu, Takashi Ipposhi, Masayuki Terai, Masaaki Iijima, Masahiro Numa

IEICE Electron. Express, 2008

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect.

Masako Fujii, Hiroaki Suzuki, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara

Proceedings of the ESSCIRC 2008, 2008

2007

Charge recycling in MTCMOS circuits with block dividing.

Akira Tada, Hiromi Notani, Genichi Tanaka, Takashi Ipposhi, Masaaki Iijima, Masahiro Numa

IEICE Electron. Express, 2007

2006

A novel power gating scheme with charge recycling.

Akira Tada, Hiromi Notani, Masahiro Numa

IEICE Electron. Express, 2006

High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI.

Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

1997

Scalable Shared-Buffering ATM Switch with a Versatile Searchable Queue.

Hideaki Yamanaka, Hirotaka Saito, Harofusa Kondoh, Yasuhito Sasaki, Hirotoshi Yamada, Munenori Tsuzuki, Satoshi Nishio, Hiromi Notani, Atsushi Iwabu, Masahiko Ishiwaki, Shigeki Kohama, Yoshio Matsuda, Kazuyoshi Oshima

IEEE J. Sel. Areas Commun., 1997

1993

A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture.

Harufusa Kondoh, Hiromi Notani, Hideaki Yamanaka, Keiichi Higashitani, Hirotaka Saito, Isamu Hayashi, Shigeki Kohama, Yoshio Matsuda, Kazuyoshi Oshima, Masao Nakaya

IEEE J. Solid State Circuits, July, 1993

1991

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture.

Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Hiromi Notani, Harufusa Kondoh, Shinpei Kayano

IEEE J. Solid State Circuits, November, 1991