Hoshik Kim

Orcid: 0000-0002-4017-8124

According to our database1, Hoshik Kim authored at least 17 papers between 2002 and 2026.

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Timeline

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Bibliography

2026
Toward Deployable CXL-PNM: The CMM-Ax Prototype and Software Stack.
IEEE Trans. Computers, April, 2026

AI+HW 2035: Shaping the Next Decade.
CoRR, March, 2026

JBOC: Just a Bunch of CXL-Enabled SSDs for Resource-Efficient LLM Checkpointing.
IEEE Comput. Archit. Lett., 2026

Near-HBM Tensor Core Acceleration for Fine-Grained Sparse Matrix-Matrix Multiplication.
IEEE Comput. Archit. Lett., 2026

H<sup>3</sup>: Hybrid Architecture Using High Bandwidth Memory and High Bandwidth Flash for Cost-Efficient LLM Inference.
IEEE Comput. Archit. Lett., 2026

2025
TraCT: Disaggregated LLM Serving with CXL Shared Memory KV Cache at Rack-Scale.
CoRR, December, 2025

Accelerating Sparse Matrix-Matrix Multiplication on GPUs with Processing Near HBMs.
CoRR, December, 2025

cMPI: Using CXL Memory Sharing for MPI One-Sided and Two-Sided Inter-Node Communications.
CoRR, October, 2025

OASIS: Object-based Analytics Storage for Intelligent SQL Query Offloading in Scientific Tabular Workloads.
CoRR, September, 2025

Improving SQL Join Algorithms for Distributed Systems: A Case Study of Compute Express Link-Based Multihost Shared Memory.
IEEE Micro, 2025

MoSKA: Mixture of Shared KV Attention for Efficient Long-Sequence LLM Inference.
IEEE Comput. Archit. Lett., 2025

StreamDQ: HBM-Integrated On-the-Fly DeQuantization via Memory Load for Large Language Models.
IEEE Comput. Archit. Lett., 2025

PNM Meets Sparse Attention: Enabling Multi-Million Tokens Inference at Scale.
IEEE Comput. Archit. Lett., 2025

cMPI: Using CXL Memory Sharing for MPI One-Sided and Two-Sided Inter-Node Communications.
Proceedings of the International Conference for High Performance Computing, 2025

Integrating Distributed SQL Query Engines with Object-Based Computational Storage.
Proceedings of the SC '25 Workshops of the International Conference for High Performance Computing, 2025

2023
Dynamic Capacity Service for Improving CXL Pooled Memory Efficiency.
IEEE Micro, 2023

2002
Relative Timing Based Verification of Timed Circuits and Systems.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002


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