Hossein Shakiba

Orcid: 0000-0002-6247-512X

According to our database1, Hossein Shakiba authored at least 24 papers between 1994 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Online presence:

On csauthors.net:

Bibliography

2026
A Ping-Pong Integrating FFE for Wireline SerDes Applications.
IEEE Open J. Circuits Syst., 2026

2025
Max-Pooling PD: A Machine Learning-Based Timing Recovery Method.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2025

MMSE Equalizer Design Optimization for Wireline SerDes Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2025

2024
A Low-Power High-BW PAM4 VCSEL Driver With Three-Tap FFE in 12-nm CMOS FinFET Process.
IEEE J. Solid State Circuits, July, 2024

A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI.
IEEE Open J. Circuits Syst., 2024

Analysis and Design of an Optimal Noise Estimation and Cancellation Filter in Wireline Communication.
IEEE Open J. Circuits Syst., 2024

A Companding Technique to Reduce Peak-to-Average Ratio in Discrete Multitone Wireline Receivers.
IEEE Open J. Circuits Syst., 2024

FBMC vs. PAM and DMT for High-Speed Wireline Communication.
IEEE Open J. Circuits Syst., 2024

An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2023
An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process.
IEEE Open J. Circuits Syst., 2023

A 0.32pJ/b 90Gbps PAM4 Optical Receiver Front-End with Automatic Gain Control in 12nm CMOS FinFET.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Efficient PAPR Reduction for Discrete Multi-Tone Signalling in High-Speed Wireline Applications.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A 0.82pJ/b 50Gb/s PAM4 VCSEL Driver with 3-Tap Asymmetric FFE in 12nm CMOS FinFET Process.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE).
IEEE Open J. Circuits Syst., 2022

A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier.
IEEE Open J. Circuits Syst., 2022

An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline Applications.
IEEE Open J. Circuits Syst., 2022

A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver.
IEEE J. Solid State Circuits, 2022

2021
Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication.
IEEE Open J. Circuits Syst., 2021

Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications.
IEEE Open J. Circuits Syst., 2021

A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

1998
Automatic swing control in relaxation oscillators.
IEEE J. Solid State Circuits, 1998

An integrated 200-MHz 3.3-V BiCMOS class-IV partial-response analog Viterbi decoder.
IEEE J. Solid State Circuits, 1998

1994
Analog Implementation of Class-IV Partial-Response Viterbi Detector.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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