Peter Krotnev

Orcid: 0000-0001-7180-0396

Affiliations:
  • Huawei Technologies Canada, Ottawa, ON, Canada


According to our database1, Peter Krotnev authored at least 7 papers between 2019 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

Online presence:

On csauthors.net:

Bibliography

2022
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver.
IEEE J. Solid State Circuits, 2022

2021
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019


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