Henry Wong

According to our database1, Henry Wong authored at least 20 papers between 1999 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2021
HD-Map Aided LiDAR-INS Extrinsic Calibration.
Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021

8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

MMW Radar-Based Technologies in Autonomous Driving: A Review.
Sensors, 2020

2019
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors.
ACM Trans. Reconfigurable Technol. Syst., 2018

2016
Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System.
ACM Trans. Reconfigurable Technol. Syst., 2016

Assessing design dependencies in modular systems.
Proceedings of the Annual IEEE Systems Conference, 2016

High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2014
Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Efficient methods for out-of-order load/store execution for high-performance soft processors.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2011
Implications of Historical Trends in the Electrical Efficiency of Computing.
IEEE Ann. Hist. Comput., 2011

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Demystifying GPU microarchitecture through microbenchmarking.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

2009
Analyzing CUDA workloads using a detailed GPU simulator.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

2008
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2004
Java threads - understanding and mastering concurrent programming: covers J2SE 5.o (3. ed.).
O'Reilly, ISBN: 978-0-596-00782-9, 2004

2000
Jini in a nutshell - a desktop quick reference.
O'Reilly, ISBN: 978-1-56592-759-9, 2000

1999
Java threads - Java 2 (2. ed.).
O'Reilly, ISBN: 978-1-56592-418-5, 1999


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