Sungpill Choi
Orcid: 0000-0002-8468-6374
According to our database1,
Sungpill Choi
authored at least 26 papers
between 2014 and 2024.
Collaborative distances:
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Bibliography
2024
2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2020
IEEE Trans. Circuits Syst., 2020
DT-CNN: An Energy-Efficient Dilated and Transposed Convolutional Neural Network Processor for Region of Interest Based Image Segmentation.
IEEE Trans. Circuits Syst., 2020
A 0.5V, 6.2μW, 0.059mm<sup>2</sup> Sinusoidal Current Generator IC with 0.088% THD for Bio-Impedance Sensing.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
CNNP-v2: A Memory-Centric Architecture for Low-Power CNN Processor on Domain-Specific Mobile Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
A 2.1TFLOPS/W Mobile Deep RL Accelerator with Transposable PE Array and Experience Compression.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
DT-CNN: Dilated and Transposed Convolution Neural Network Accelerator for Real-Time Image Segmentation on Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
CNNP-v2: An Energy Efficient Memory-Centric Convolutional Neural Network Processor Architecture.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
A Low-Power Convolutional Neural Network Face Recognition Processor and a CIS Integrated With Always-on Face Detector.
IEEE J. Solid State Circuits, 2018
A 9.02mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 46.1 fps Global Matching Optical Flow Estimation Processor for Action Recognition in Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Micro, 2017
14.6 A 0.62mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detector.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
An ultra-low-power and mixed-mode event-driven face detection SoC for always-on mobile applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
A CMOS Image Sensor-Based Stereo Matching Accelerator With Focal-Plane Sparse Rectification and Analog Census Transform.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
14.1 A 126.1mW real-time natural UI/UX processor with embedded deep-learning core for low-power smart glasses.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A 43.7 mW 94 fps CMOS image sensor-based stereo matching accelerator with focal-plane rectification and analog census transformation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A 34pJ/level pixel depth-estimation processor with shifter-based pipelined architecture for mobile user interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
An Energy-Efficient and Scalable Deep Learning/Inference Processor With Tetra-Parallel MIMD Architecture for Big Data Applications.
IEEE Trans. Biomed. Circuits Syst., 2015
4.6 A1.93TOPS/W scalable deep learning/inference processor with tetra-parallel MIMD architecture for big-data applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 124.9fps memory-efficient hand segmentation processor for hand gesture in mobile devices.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE International Conference on Industrial Technology, 2015
2014
10.4 A 1.22TOPS and 1.52mW/MHz augmented reality multi-core processor with neural network NoC for HMD applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014