Chang-Hyo Yu
According to our database1,
Chang-Hyo Yu
authored at least 22 papers
between 2003 and 2024.
Collaborative distances:
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Bibliography
2024
2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2013
72.5GFLOPS 240Mpixel/s 1080p 60fps multi-format video codec application processor enabled with GPGPU for fused multimedia application.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2011
A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache.
IEEE Trans. Very Large Scale Integr. Syst., 2011
2009
A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Comput. Graph., 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine.
IEEE J. Solid State Circuits, 2008
A 3D graphics processor with fast 4D vector inner product units and power aware texture cache.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches.
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
An adaptive spatial filter for early depth test.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
A hierarchical depth buffer for minimizing memory bandwidth in 3D rendering engine: Depth Filter.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A hardware-like high-level language based environment for 3D graphics architecture exploration.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003