Hyeongmin Seo

According to our database, Hyeongmin Seo authored at least 7 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS.

Wookjin Shin, Hyeongmin Seo, Sangwan Lee, Dong-Ho Choi, Young-Ho Kwak, Soon-Jae Won, Jaeduk Han

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology.

Taeyang Sim, Sun-Ho Yeom, Hyunwoo Im, Youngmin Oh, Hyeongmin Seo, Hyeongjun Ko, Hankyu Chi, Hae-Kang Jung, Jaeduk Han

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

A 35-Gb/s PAM-4 Transmitter With 7B4Q Full-Transition Avoidance and Area-Efficient Gm-Boosting Techniques.

Eunji Song, Jiyun Han, Hyeongmin Seo, Hyuntae Kim, Hyunwoo Im, Jaeduk Han

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023

Digital Forensic Research for Analyzing Drone Pilot: Focusing on DJI Remote Controller.

Sungwon Lee, Hyeongmin Seo, Dohyun Kim

Sensors, November, 2023

A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS.

Hyochang Kim, Hyeongmin Seo, Hyuntae Kim, Changsik Yoo, Jaeduk Han

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS.

Hyuntae Kim, Hyeongmin Seo, Yunseong Jo, Changsik Yoo, Jaeduk Han

IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend.

Hyeongmin Seo, Jiyun Han, Kyungmin Kim, Baek-Jin Lim, EunSeok Shin, Youngdon Choi, Hyungjong Ko, Jung-Hwan Choi, Sang-Hyun Lee, Changsik Yoo, Jaeduk Han

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023