Hyochang Kim
Orcid: 0000-0002-8360-4103Affiliations:
- Samsung Electronics, Memory Division, Hwaseong, Korea
- Hanyang University, Department of Electronics Engineering, Seoul, Korea (PhD 2019)
According to our database1,
Hyochang Kim authored at least 6 papers
between 2012 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2023
A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.
IEEE J. Solid State Circuits, 2023
2020
A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2020
2017
IEICE Electron. Express, 2017
2016
A HDMI-to-MHL video format conversion system-on-chip (SoC) for mobile handset in a 130-nm CMOS technology.
Proceedings of the IEEE International Conference on Consumer Electronics, 2016
2012
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012