Hyun J. Shin

According to our database, Hyun J. Shin authored at least 6 papers between 1994 and 2004.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2004

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link.

Yongsam Moon, Young-Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog-Kyoon Jeong

IEEE J. Solid State Circuits, 2004

1999

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface.

Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada

IEEE J. Solid State Circuits, 1999

1996

Single-chip 4×500-MBd CMOS transceiver.

Albert X. Widmer, Kevin R. Wrenner, Herschel A. Ainspan, Ben Parker, Pierre Austruy, Bernard Brezzo, Anne-Marie Haen, John F. Ewen, Mehmet Soyuer, Alain Blanc, Jean-Claude Abbiate, Alina Deutsch, Hyun J. Shin

IEEE J. Solid State Circuits, 1996

1995

Digital FIR filters for high speed PRML disk read channels.

Dale J. Pearson, Scott K. Reynolds, Andrew C. Megdanis, Sudhir M. Gowda, Kevin R. Wrenner, Michael Immediato, Richard L. Galbraith, Hyun J. Shin

IEEE J. Solid State Circuits, December, 1995

Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications.

Hyun J. Shin, Dale J. Pearson, Scott K. Reynolds, Andrew C. Megdanis, Sudhir M. Gowda, Kevin R. Wrenner

IBM J. Res. Dev., 1995

1994

A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits.

Hyun J. Shin

IEEE J. Solid State Circuits, April, 1994