Inhwa Jung

According to our database1, Inhwa Jung authored at least 22 papers between 2005 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel.
IEEE J. Solid State Circuits, 2015

2014
A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile.
IEEE J. Solid State Circuits, 2012

A TDC-based skew compensation technique for high-speed output driver.
Proceedings of the International SoC Design Conference, 2012

A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 µs Frequency Acquisition Time.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A 0.076mm<sup>2</sup> 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A Gb/s+ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

2009
A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008
A 0.004-mm<sup>2</sup> Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A slew-rate controlled output driver with one-cycle tuning time.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

A 1.2GHz delayed clock generator for high-speed microprocessors.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Noise-Aware Split-Path Domino Logic and its Clock Delaying Scheme.
J. Circuits Syst. Comput., 2007

Sptpl: a New Pulsed Latch Type Flip-Flop in High-Performance System-on-a-Chip (SOC).
J. Circuits Syst. Comput., 2007

A One-Cycle Lock Time Slew-Rate-Controlled Output Driver.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A New Energy x Delay-Aware Flip-Flop.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

2005
Differential Pass Transistor Pulsed Latch.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005


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