Jong-Sam Kim
According to our database1,
Jong-Sam Kim
authored at least 6 papers
between 2009 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.
IEEE J. Solid State Circuits, 2020
2019
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2014
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.
IEEE J. Solid State Circuits, 2012
2009
A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control.
IEEE J. Solid State Circuits, 2009