Jaewoo Park

Affiliations:

Samsung Electronics, Memory Division, Hwaseong, South Korea

According to our database¹, Jaewoo Park authored at least 6 papers between 2021 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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Bibliography

2025

22.4 A 32-to-50Gb/s/pin Single-Ended PAM-4 Transmitter with a ZQ-Based FFE and PAM-4 LSB DBI-DC Encoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, October, 2024

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023

A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2021

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics.

[BibT_eX]

[DOI]

Proceedings of the 47th ESSCIRC 2021, 2021

Jaewoo Park

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