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Jaihyuk Song

According to our database¹, Jaihyuk Song authored at least 16 papers between 2023 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Links

On csauthors.net:

Bibliography

2026

A 1.16 e-rms Temporal Random Noise, 123-dB High Dynamic Range, 2.988-μm Pitch 3-Mpixel Three-Stacked Digital Pixel Sensor for Versatile Applications.

[DOI]

IEEE J. Solid State Circuits, April, 2026

A 1.09e<sup>-</sup>-Random-Noise 1.5μm-Pixel-Pitch 12MP Global-Shutter-Equivalent CMOS Image Sensor with 3μm Digital Pixels Using Quad-Phase-Staggered Zigzag Readout and Motion Compensation.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

AI Revolution Driven by Memory Technology Innovation.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

6.1 A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2µm -Pitch 50Mpixel Rolling Shutter and 2.4µm -Pitch 12.5Mpixel Global Shutter Modes for Mobile Applications.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

A Study on the Origin of Dynamic Charge Loss of Next Generation DRAM Cell Array Transistor.

[DOI]

Moonyoung Jeong

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Proceedings of the IEEE International Reliability Physics Symposium, 2025

Future Technology Outlook on DRAM/Flash Memories for More Moore and More Than Moore.

[DOI]

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Young Guen Song

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Proceedings of the IEEE International Memory Workshop, 2025

2024

Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch.

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Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Cell to Core-Periphery Overlap (C2O) Based on BCAT for Next Generation DRAM.

[DOI]

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Moonyoung Jeong

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Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A Metal Dual Work-Function Gate (MDWG) for the Continuous Scaling of DRAM Cell Transistors.

[DOI]

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Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Expanding Design Technology Co-Optimization Potentials with Back-Side Interconnect Innovation.

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Muhammed Ahosan Ul Karim

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Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

6.10 A 1/1.56-inch 50Mpixel CMOS Image Sensor with 0.5μm pitch Quad Photodiode Separated by Front Deep Trench Isolation.

[DOI]

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Kyoung Eun Chang

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Byung Seok Moon

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Chong Kwang Chang

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Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND.

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Proceedings of the IEEE International Reliability Physics Symposium, 2024

A Novel Quantitative Model for Combination Effects of Hydrogen and Process Heat on Peripheral Transistors in 3D-NAND Flash Memory.

[DOI]

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Proceedings of the IEEE International Reliability Physics Symposium, 2024

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET.

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Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023

Trends and Future Challenges of 3D NAND Flash Memory.

[DOI]

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Proceedings of the IEEE International Memory Workshop, 2023

Improvement of GIDL-assisted Erase by using Surrounded BL PAD Structure for VNAND.

[DOI]

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Proceedings of the IEEE International Memory Workshop, 2023

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