Jaeyong Jeong

Orcid: 0000-0003-1309-0490

According to our database1, Jaeyong Jeong authored at least 18 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2024
First Heterogeneous and Monolithic 3D (HM3D) Integration of InGaAs HEMTs and InP/InGaAs DHBTs on Si CMOS for Next-Generation Wireless Communication.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Ge(110) GAA Nanosheet / Si(100) Tri-gate Nanosheet Monolithic CFETs Featuring Record-High Hole Mobility.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A Valid Experimental Design of the Lifetime Prediction for NAND Cell Oxide.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

NORNS: Three Guides for Efficient Automatic Post-Fabrication Optimization of Modern NAND Flash Memory.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

2023
Kernel Smoothing Technique Based on Multiple-Coordinate System for Screening Potential Failures in NAND Flash Memory.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Cryogenic RF Transistors and Routing Circuits Based on 3D Stackable InGaAs HEMTs with Nb Superconductors for Large-Scale Quantum Signal Processing.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
3D stackable cryogenic InGaAs HEMTs for heterogeneous and monolithic 3D integrated highly scalable quantum computing systems.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A sub-micron-thick InGaAs broadband (400-1700 nm) photodetectors with a high external quantum efficiency (>70%).
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
An immersed interface method for acoustic wave equations with discontinuous coefficients in complex geometries.
J. Comput. Phys., 2021

2017
Dynamic Erase Voltage and Time Scaling for Extending Lifetime of NAND Flash-Based SSDs.
IEEE Trans. Computers, 2017

2016
An Integrated Approach for Managing Read Disturbs in High-Density NAND Flash Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Improving performance and lifetime of NAND storage systems using relaxed program sequence.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Flashdefibrillator: a data recovery technique for retention failures in NAND flash memory.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

2014
Lifetime improvement of NAND flash-based storage systems using dynamic program and erase scaling.
Proceedings of the 12th USENIX conference on File and Storage Technologies, 2014

2013
Improving NAND Endurance by Dynamic Program and Erase Scaling.
Proceedings of the 5th USENIX Workshop on Hot Topics in Storage and File Systems, 2013

A read-disturb management technique for high-density NAND flash memory.
Proceedings of the Asia-Pacific Workshop on Systems, 2013

2012
A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface.
IEEE J. Solid State Circuits, 2012

A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory.
Proceedings of the Symposium on VLSI Circuits, 2012


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