Kwang-Il Park

According to our database1, Kwang-Il Park authored at least 43 papers between 1997 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques.
IEEE J. Solid State Circuits, 2020

A Methodology Combining Cosine Similarity with Classifier for Text Classification.
Appl. Artif. Intell., 2020


22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
IEEE J. Solid State Circuits, 2019

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM.
IEEE J. Solid State Circuits, 2018

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018



An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017


Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017


2016
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.
IEEE J. Solid State Circuits, 2015

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
HMM and Rule-Based Hybrid Intruder Detection Approach by Synthesizing Decisions of Sensors.
Int. J. Distributed Sens. Networks, 2013

2012
A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface.
IEEE J. Solid State Circuits, 2012

2011
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.
IEEE J. Solid State Circuits, 2011


2010
Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232].
IEEE J. Solid State Circuits, 2010


A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme.
IEEE J. Solid State Circuits, 2009

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces.
IEEE J. Solid State Circuits, 2009

A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN.
IEEE J. Solid State Circuits, 2009

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.
IEEE J. Solid State Circuits, 2008

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A DLL with Jitter-Reduction Techniques for DRAM Interfaces.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


2000
A Wormhole Router with Embedded Broadcasting Virtual Bus for Mesh Computers.
Parallel Process. Lett., 2000

1999
A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting.
Proceedings of the International Conference on Parallel Processing 1999, 1999

1998
Event suppression by optimizing VHDL programs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998


1997
The Acceleration of VHDL Simulation by Classifying Events.
Proceedings of the Proceedings 30st Annual Simulation Symposium (SS '97), April 7-9, 1997, 1997


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