Young-Hyun Jun
According to our database1,
Young-Hyun Jun
authored at least 76 papers
between 1989 and 2017.
Collaborative distances:
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Bibliography
2017
A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface.
IEEE J. Solid State Circuits, 2017
2015
10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEICE Electron. Express, 2014
2013
Accurate quadruple-gamma-curve correction for line inversion-based mobile TFT-LCD driver ICS.
IEEE Trans. Consumer Electron., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Fast Output Voltage-Regulated PWM Buck Converter With an Adaptive Ramp Amplitude Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH.
IEEE J. Solid State Circuits, 2013
Blind-oversampling adaptive oversample-level DFE receiver for unsynchronized global on-chip serial links.
IEICE Electron. Express, 2013
IEICE Electron. Express, 2013
A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications.
IEICE Electron. Express, 2013
2012
A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface.
IEEE J. Solid State Circuits, 2012
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking.
IEEE J. Solid State Circuits, 2012
IEICE Trans. Electron., 2012
A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Adaptive frequency-controlled ultra-fast hysteretic buck converter for portable devices.
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.
IEEE J. Solid State Circuits, 2011
Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM.
IEEE J. Solid State Circuits, 2011
An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs.
IEICE Trans. Electron., 2011
IEICE Trans. Electron., 2011
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the Control and Automation, and Energy System Engineering, 2011
Line inversion-based mobile TFT-LCD driver IC with accurate quadruple-gamma-curve correction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
IEEE Trans. Consumer Electron., 2010
A 31 ns Random Cycle VCAT-Based 4F <sup>2</sup> DRAM With Manufacturability and Enhanced Cell Efficiency.
IEEE J. Solid State Circuits, 2010
Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232].
IEEE J. Solid State Circuits, 2010
IEEE J. Solid State Circuits, 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme.
IEEE J. Solid State Circuits, 2009
A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces.
IEEE J. Solid State Circuits, 2009
A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN.
IEEE J. Solid State Circuits, 2009
IEICE Electron. Express, 2009
1.2V 1.6Gb/s 56nm 6F<sup>2</sup> 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
45nm Low-power Embedded Pseudo-SRAM with ECC-based Auto-adjusted Self-refresh Scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
IEEE J. Solid State Circuits, 2008
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.
IEEE J. Solid State Circuits, 2008
IEICE Electron. Express, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Microelectron. J., 2007
IEICE Trans. Electron., 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
J. Inf. Process. Syst., 2006
2005
IEEE J. Solid State Circuits, 2005
A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2001
IEEE J. Solid State Circuits, 2001
2000
Data-dependent evaluating latched CMOS differential logic family for statistical power reduction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1993
A New Colum Redundancy Scheme For Fast Access Time of 64-Mb DRAM.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
1990
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
1989
An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989