Javier Verdú

Orcid: 0000-0003-4485-2419

According to our database1, Javier Verdú authored at least 21 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Transfer-Learning-Based Intrusion Detection Framework in IoT Networks.
Sensors, 2022

2021
A cost-efficient QoS-aware analytical model of future software content delivery networks.
Int. J. Netw. Manag., 2021

Deep Learning Detection of GPS Spoofing.
Proceedings of the Machine Learning, Optimization, and Data Science, 2021

2018
Platform-Agnostic Steal-Time Measurement in a Guest Operating System.
CoRR, 2018

2016
Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach.
IEEE Trans. Computers, 2016

Dynamic web worker pool management for highly parallel javascript web applications.
Concurr. Comput. Pract. Exp., 2016

Performance Scalability Analysis of JavaScript Applications with Web Workers.
IEEE Comput. Archit. Lett., 2016

2013
Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors.
IEEE Trans. Parallel Distributed Syst., 2013

2012
The Problem of Evaluating CPU-GPU Systems with 3D Visualization Applications.
IEEE Micro, 2012

Optimal task assignment in multithreaded processors: a statistical approach.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2011
An Abstraction Methodology for the Evaluation of Multi-core Multi-threaded Architectures.
Proceedings of the MASCOTS 2011, 2011

2010
Thread to strand binding of parallel network applications in massive multi-threaded systems.
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010

2009
Characterizing the resource-sharing levels in the UltraSPARC T2 processor.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

2008
Analysis and architectural support for parallel stateful packet processing.
PhD thesis, 2008

Measuring Operating System Overhead on CMT Processors.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

MultiLayer processing - an execution model for parallel stateful packet processing.
Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2008

2005
The impact of traffic aggregation on the memory performance of networking applications.
SIGARCH Comput. Archit. News, 2005

Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

Workload Characterization of Stateful Networking Applications.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Architectural impact of stateful networking applications.
Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2005

2004
The impact of traffic aggregation on the memory performance of networking applications.
Proceedings of the 2004 workshop on MEmory performance, 2004


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