Petar Radojkovic

Orcid: 0000-0002-9334-3330

According to our database1, Petar Radojkovic authored at least 29 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
$\mathcal{O}(n)$O(n) Key-Value Sort With Active Compute Memory.
IEEE Trans. Computers, May, 2024

2022
Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation.
ACM Trans. Embed. Comput. Syst., 2022

2020
Cost-aware prediction of uncorrected DRAM errors in the field.
Proceedings of the International Conference for High Performance Computing, 2020

2019
PROFET: Modeling System Performance and Energy Without Simulating the CPU.
Proc. ACM Meas. Anal. Comput. Syst., 2019

DRAM errors in the field: a statistical approach.
Proceedings of the International Symposium on Memory Systems, 2019

Rethinking cycle accurate DRAM simulation.
Proceedings of the International Symposium on Memory Systems, 2019

STT-MRAM for real-time embedded systems: performance and WCET implications.
Proceedings of the International Symposium on Memory Systems, 2019

Towards resilient EU HPC systems: a blueprint.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

Main memory latency simulation: the missing link.
Proceedings of the International Symposium on Memory Systems, 2018

HPC Benchmarking: Scaling Right and Looking Beyond the Average.
Proceedings of the Euro-Par 2018: Parallel Processing, 2018

2017
Main Memory in HPC: Do We Need More or Could We Live with Less?
ACM Trans. Archit. Code Optim., 2017

Enabling a reliable STT-MRAM main memory simulation.
Proceedings of the International Symposium on Memory Systems, 2017

Microbenchmarks for Detailed Validation and Tuning of Hardware Simulators.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach.
IEEE Trans. Computers, 2016

Large-Memory Nodes for Energy Efficient High-Performance Computing.
Proceedings of the Second International Symposium on Memory Systems, 2016

Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC.
Proceedings of the Second International Symposium on Memory Systems, 2016

2015
Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?
Proceedings of the 2015 International Symposium on Memory Systems, 2015

Limpio: LIghtweight MPI instrumentatiOn.
Proceedings of the 2015 IEEE 23rd International Conference on Program Comprehension, 2015

2014
Energy Efficient HPC on Embedded SoCs: Optimization Techniques for Mali GPU.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

2013
Improving the effective use of multithreaded architectures : implications on compilation, thread assignment, and timing analysis.
PhD thesis, 2013

Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors.
IEEE Trans. Parallel Distributed Syst., 2013

2012
On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments.
ACM Trans. Archit. Code Optim., 2012

Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Optimal task assignment in multithreaded processors: a statistical approach.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2010
Thread to strand binding of parallel network applications in massive multi-threaded systems.
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010

2009
Characterizing the resource-sharing levels in the UltraSPARC T2 processor.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

2008
Measuring Operating System Overhead on CMT Processors.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008


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