Max Doblas

According to our database, Max Doblas authored at least 8 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

WFA-GPU: gap-affine pairwise read-alignment using GPUs.

Quim Aguado-Puig, Max Doblas, Christos Matzoros, Antonio Espinosa, Juan Carlos Moure, Santiago Marco-Sola, Miquel Moretó

Bioinform., December, 2023

GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment.

Max Doblas, Oscar Lostes-Cazorla, Quim Aguado-Puig, Nick Cebry, Pau Fontova-Musté, Christopher Frances Batten, Santiago Marco-Sola, Miquel Moretó

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

WFAsic: A High-Performance ASIC Accelerator for DNA Sequence Alignment on a RISC-V SoC.

Abbas Haghi, Lluc Alvarez, Jordi Fornt, Juan Miguel De Haro Ruiz, Roger Figueras, Max Doblas, Santiago Marco-Sola, Miquel Moretó

Proceedings of the 52nd International Conference on Parallel Processing, 2023

Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices.

Enrico Reggiani, Alessandro Pappalardo, Max Doblas, Miquel Moretó, Mauro Olivieri, Osman Sabri Unsal, Adrián Cristal

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology.

Max Doblas, Gerard Candón, Xavier Carril, Marc Domínguez, Enric Erra, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Josep Oltra, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Hugo Safadi, Víctor Soria, Alejandro Suanes, Iván Vargas, Fernando Arreza, Roger Figueras, Pau Fontova-Musté, Joan Marimon, Ricardo Martínez, Sergio Moreno, Jordi Sacristán, Oscar Alonso, Xavier Aragonès, Adrián Cristal, Ángel Diéguez, Manuel López, Diego Mateo, Francesc Moll, Miquel Moretó, Oscar Palomar, Marco A. Ramírez, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luis Villa

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022

Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI.

Víctor Soria Pardos, Max Doblas, Guillem López-Paradís, Gerard Candón, Narcís Rodas, Xavier Carril, Pau Fontova-Musté, Neiel Leyva, Santiago Marco-Sola, Miquel Moretó

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology.

Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio, Jordi Sacristán, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luís Villa

Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2020

An Academic RISC-V Silicon Implementation Based on Open-Source Components.

Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, Ricardo Martínez, Jonnatan Mendoza, Francesc Moll, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Marco Antonio Ramírez, Carlos Rojas Morales, Antonio Rubio, Abraham Ruiz, Nehir Sönmez, Víctor Soria, Lluís Terés, Osman S. Unsal, Mateo Valero, Iván Vargas Valdivieso, Luis Villa

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020