Jean-François Naviner

Orcid: 0000-0001-8445-9860

According to our database1, Jean-François Naviner authored at least 51 papers between 1990 and 2016.

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Bibliography

2016
Efficient reliability evaluation methodologies for combinational circuits.
Microelectron. Reliab., 2016

2015
Cross-layer investigation of continuous-time sigma-delta modulator under aging effects.
Microelectron. Reliab., 2015

2014
A hybrid reliability assessment method and its support of sequential logic modelling.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013
SNaP: A novel hybrid method for circuit reliability assessment under multiple faults.
Microelectron. Reliab., 2013

Selective hardening against multiple faults employing a net-based reliability analysis.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Single event transient mitigation through pulse quenching: Effectiveness at circuit level.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology.
Proceedings of Eurocon 2013, 2013

Reliability analysis of combinational circuits with the influences of noise and single-event transients.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Exploring the feasibility of selective hardening for combinational logic.
Microelectron. Reliab., 2012

A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems.
J. Low Power Electron., 2012

Reliability analysis of a Reed-Solomon decoder.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Selective hardening methodology for combinational logic.
Proceedings of the 13th Latin American Test Workshop, 2012

Automatic selective hardening against soft errors: A cost-based and regularity-aware approach.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
FIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level.
Microelectron. Reliab., 2011

A synthesis methodology for AMS/RF circuit reliability: Application to a DCO design.
Microelectron. Reliab., 2011

Reliability aware design of low power continuous-time sigma-delta modulator.
Microelectron. Reliab., 2011

A new synthesis methodology for reliable RF front-end Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Using error tolerance of target application for efficient reliability improvement of digital circuits.
Microelectron. Reliab., 2010

An efficient tool for reliability improvement based on TMR.
Microelectron. Reliab., 2010

On evaluating the signal reliability of self-checking arithmetic circuits.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

AMS and RF design for reliability methodology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008
Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Relevant metrics for evaluation of concurrent error detection schemes.
Microelectron. Reliab., 2008

Signal probability for reliability evaluation of logic circuits.
Microelectron. Reliab., 2008

A Novel Approach to Non Coherent UWB Reception.
Proceedings of the Wireless Networks, 2008

On the output events in concurrent error detection schemes.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Reliability analysis of logic circuits based on signal probability.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Methods and Metrics for Reliability Assessment.
Proceedings of the Fault-Tolerant Distributed Algorithms on VLSI Chips, 07.09., 2008

2006
Yield and reliability issues in nanoelectronic technologies.
Ann. des Télécommunications, 2006

A CMOS implementation of time-interleaved high-pass Delta Sigma modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-pass Delta Sigma modulator: from system analysis to circuit design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Impact of charge injection on system-level performance of a discrete-time GSM receiver.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Calibration of sampling instants in a multiple channel time-interleaved analog-to-digital converter.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
Systems-on-chip for telecommunications.
Ann. des Télécommunications, 2004

Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

2003
Designing a programmable analog signal conditioning circuit without loss of measurement range.
IEEE Trans. Instrum. Meas., 2003

Temporel and spectral analysis of time interleaved high pass sigma delta converter.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2002
Analog to digital conversion: technical aspects.
Ann. des Télécommunications, 2002

Analysis of time-interleaved delta-sigma analog to digital converter.
Proceedings of the 55th IEEE Vehicular Technology Conference, 2002

A time-interleaved chopper-stabilized delta-sigma analog to digital converter.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

An interleaved delta-sigma analog to digital converter with digital correction.
Proceedings of the IEEE International Conference on Acoustics, 2002

2001
Trade-off between antialiasing filter and analog-to-digital converters specifications in homodyne radio frequency receivers.
Proceedings of the 54th IEEE Vehicular Technology Conference, 2001

A switched-current sample and hold circuit for low frequency applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Antialiasing filtering influences on ADC specifications for radio receivers.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1999
A track&hold-mixer for direct-conversion by subsampling.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1994
An Optimizable Model for Process Independent Symbolic Design.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Préforme/aGAPE: a synergy between symbolic cell design and assembly.
Microprocess. Microprogramming, 1993

1990
Preform: A Process Independent Symbolic Layout System.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990


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