Jeremy Casas

Orcid: 0000-0002-0890-7673

According to our database1, Jeremy Casas authored at least 12 papers between 1994 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Correct-by-Construction Design of Custom Accelerator Microarchitectures.
IEEE Trans. Computers, January, 2024

2023
Towards A Correct-by-Construction FHE Model.
IACR Cryptol. ePrint Arch., 2023

An Automated Verification Framework for HalideIR-Based Compiler Transformations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Invited: A Scalable Formal Approach for Correctness-Assured Hardware Design.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Towards A Formally Verified Fully Homomorphic Encryption Compute Engine.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Accelerator design with decoupled hardware customizations: benefits and challenges: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2003
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Reasoning about GSTE Assertion Graphs.
Proceedings of the Correct Hardware Design and Verification Methods, 2003

2000
A switch level fault simulation environment.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Logic Verification of Very Large Circuits Using Shark.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1995
MPVM: A Migration Transparent Version of PVM.
Comput. Syst., 1995

1994
Adaptive load migration systems for PVM.
Proceedings of the Proceedings Supercomputing '94, 1994


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