Yi-Hsiang Lai

Orcid: 0000-0002-2358-805X

According to our database1, Yi-Hsiang Lai authored at least 15 papers between 2014 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
AdaServe: Accelerating Multi-SLO LLM Serving with SLO-Customized Speculative Decoding.
Proceedings of the 21st European Conference on Computer Systems, 2026

2024
Automated Deep Learning Optimization via DSL-Based Source Code Transformation.
Proceedings of the 33rd ACM SIGSOFT International Symposium on Software Testing and Analysis, 2024

2022
HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Accelerator design with decoupled hardware customizations: benefits and challenges: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects.
ACM Trans. Reconfigurable Technol. Syst., 2021

Bring Your Own Codegen to Deep Learning Compiler.
CoRR, 2021

2020
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2016
Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Asynchronous QDI Circuit Synthesis from Signal Transition Protocols.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014


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