Yi-Hsiang Lai

According to our database, Yi-Hsiang Lai authored at least 13 papers between 2014 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs.

Shaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen, Niansong Zhang, Debjit Pal, Zhiru Zhang

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Accelerator design with decoupled hardware customizations: benefits and challenges: invited.

Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects.

Yi-Hsiang Lai, Ecenur Ustun, Shaojie Xiang, Zhenman Fang, Hongbo Rong, Zhiru Zhang

ACM Trans. Reconfigurable Technol. Syst., 2021

Bring Your Own Codegen to Deep Learning Compiler.

Zhi Chen, Cody Hao Yu, Trevor Morris, Jorn Tuyls, Yi-Hsiang Lai, Jared Roesch, Elliott Delaye, Vin Sharma, Yida Wang

CoRR, 2021

2020

SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs.

Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.

Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs.

Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2016

Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits.

Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits.

Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis.

Chun-Hong Shih, Yi-Hsiang Lai, Jie-Hong Roland Jiang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines.

Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Asynchronous QDI Circuit Synthesis from Signal Transition Protocols.

Bo-Yuan Huang, Yi-Hsiang Lai, Jie-Hong Roland Jiang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits.

Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang

Proceedings of the 51st Annual Design Automation Conference 2014, 2014