Zhenkun Yang

Orcid: 0000-0001-7567-2870

According to our database1, Zhenkun Yang authored at least 41 papers between 2007 and 2024.

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Bibliography

2024
Correct-by-Construction Design of Custom Accelerator Microarchitectures.
IEEE Trans. Computers, January, 2024

2023
Multigrained Hybrid Neural Network for Rotating Machinery Fault Diagnosis Using Joint Local and Global Information.
IEEE Trans. Instrum. Meas., 2023

Towards A Correct-by-Construction FHE Model.
IACR Cryptol. ePrint Arch., 2023

Certifying Sequential Consistency of Machine Learning Accelerators.
Proceedings of the Formal Methods and Software Engineering, 2023

LCL: A Lock Chain Length-based Distributed Algorithm for Deadlock Detection and Resolution.
Proceedings of the 39th IEEE International Conference on Data Engineering, 2023

A Design Method of Aero-Engine Labyrinth Seal Parameters Based on AGA-BP Neural Network.
Proceedings of the International Conference on Advanced Robotics and Mechatronics, 2023

An Automated Verification Framework for HalideIR-Based Compiler Transformations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Invited: A Scalable Formal Approach for Correctness-Assured Hardware Design.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Towards A Formally Verified Fully Homomorphic Encryption Compute Engine.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

An Equivalence Checking Framework for Agile Hardware Design.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
OceanBase: A 707 Million tpmC Distributed Relational Database System.
Proc. VLDB Endow., 2022

Methods and Datasets of Text to Image Synthesis Based on Generative Adversarial Network.
Proceedings of the 5th IEEE International Conference on Information Systems and Computer Aided Education, 2022

Accelerator design with decoupled hardware customizations: benefits and challenges: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

FirVer: Concolic Testing for Systematic Validation of Firmware Binaries.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration.
CoRR, 2021

Dense short connection network for efficient image classification.
Concurr. Comput. Pract. Exp., 2021

Multiscale Feature Filtering Network for Image Recognition System in Unmanned Aerial Vehicle.
Complex., 2021

2020
Anti-swing strategy of overhead cranes based on prescribed performance PID control.
Int. J. Wirel. Mob. Comput., 2020

Automated Bug Detection and Replay for COTS Linux Kernel Modules with Concolic Execution.
Proceedings of the 27th IEEE International Conference on Software Analysis, 2020

UEFI Firmware Fuzzing with Simics Virtual Platform.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Asymmetric Convolution Networks Based on Multi-feature Fusion for Object Detection.
Proceedings of the 16th IEEE International Conference on Automation Science and Engineering, 2020

2019
Hardware/Software Co-monitoring.
CoRR, 2019

A Novel Data-Driven Fault Classification Method and its Application to DC Motor.
Proceedings of the IEEE International Conference on Industrial Technology, 2019

End-to-End Concolic Testing for Hardware/Software Co-Validation.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

2018
Concolic testing of SystemC designs.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

CRETE: A Versatile Binary-Level Concolic Testing Framework.
Proceedings of the Fundamental Approaches to Software Engineering, 2018

2016
Schedulability analysis of non-preemptive strictly periodic tasks in multi-core real-time systems.
Real Time Syst., 2016

OpenRISC System-on-Chip Design Emulation.
CoRR, 2016

Validating scheduling transformation for behavioral synthesis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Generating high coverage tests for SystemC designs using symbolic execution.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Automatic fault injection for driver robustness testing.
Proceedings of the 2015 International Symposium on Software Testing and Analysis, 2015

2014
Validating direct memory access interfaces with conformance checking.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Coverage evaluation of post-silicon validation tests with virtual prototypes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Scalable Certification Framework for Behavioral Synthesis Front-End.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
A Scalable, Continuously Available Database System Based on Commodity Hardware.
Proceedings of the Web-Age Information Management, 2013

Equivalence checking for compiler transformations in behavioral synthesis.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Handling design and implementation optimizations in equivalence checking for behavioral synthesis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2010
Automated synthesis of passive analog filters using graph representation.
Expert Syst. Appl., 2010

2007
Automatic Modeling of Complex Functions with Clonal Selection-Based Gene Expression Programming.
Proceedings of the Third International Conference on Natural Computation, 2007

Optimal Components Selection for Analog Active Filters Using Clonal Selection Algorithms.
Proceedings of the Advanced Intelligent Computing Theories and Applications. With Aspects of Theoretical and Methodological Issues, 2007

Automatic Synthesis of Practical Passive Filters Using Clonal Selection Principle-Based Gene Expression Programming.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2007


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