Debjit Pal

Orcid: 0000-0003-3722-5126

According to our database1, Debjit Pal authored at least 21 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
VeriBug: An Attention-based Framework for Bug-Localization in Hardware Designs.
CoRR, 2024

Formal Verification of Source-to-Source Transformations for HLS.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023
SCAR: Power Side-Channel Analysis at RTL-Level.
CoRR, 2023

FCCM 2023 PhD Student Forum Compendium of Abstracts: Held on 9th May, 2023, at Los Angeles, USA.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Accelerator design with decoupled hardware customizations: benefits and challenges: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Feature Engineering for Scalable Application-Level Post-Silicon Debugging.
CoRR, 2021

GLAIVE: Graph Learning Assisted Instruction Vulnerability Estimation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Assertion Ranking Using RTL Source Code Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Scalable functional validation of next generation SoCs
PhD thesis, 2019

A figure of merit for assertions in verification.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Application level hardware tracing for scaling post-silicon debug.
Proceedings of the 55th Annual Design Automation Conference, 2018

A cloud based autonomous multipurpose system with self-communicating bots and swarm of drones.
Proceedings of the IEEE 8th Annual Computing and Communication Workshop and Conference, 2018

A low cost fully autonomous GPS (Global Positioning System) based quad copter for disaster management.
Proceedings of the IEEE 8th Annual Computing and Communication Workshop and Conference, 2018

2016
Symptomatic Bug Localization for Functional Debug of Hardware Designs.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015
Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2013
Using automatically generated invariants for regression testing and bug localization.
Proceedings of the 2013 28th IEEE/ACM International Conference on Automated Software Engineering, 2013

2012
A Library for Passive Online Verification of Analog and Mixed-Signal Circuits.
Proceedings of the 25th International Conference on VLSI Design, 2012

2011
Chassis: A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models.
ACM Trans. Design Autom. Electr. Syst., 2011


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