Zhi-Hui Kong

According to our database1, Zhi-Hui Kong authored at least 35 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI.
IEEE J. Solid State Circuits, 2019

2017
A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control for Wireless Power Transmission.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell.
IEEE Trans. Inf. Forensics Secur., 2015

Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Statistical analysis and design of 6T SRAM cell for physical unclonable function with dual application modes.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 57 to 66 GHz novel six-port correlator.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Exploiting Process Variations and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions.
IEEE Trans. Inf. Forensics Secur., 2014

A Monolithically Integrated Pressure/Oxygen/Temperature Sensing SoC for Multimodality Intracranial Neuromonitoring.
IEEE J. Solid State Circuits, 2014

Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Leakage-resilient memory-based physical unclonable function using phase change material.
Proceedings of the International Carnahan Conference on Security Technology, 2014

2013
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing.
IEEE Trans. Very Large Scale Integr. Syst., 2013

NBTI/PBTI-Aware WWL Voltage Control for Half-Selected Cell Stability Improvement.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

PCKGen: A Phase Change Memory based cryptographic key generator.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A current-mode stimulator circuit with two-step charge balancing background calibration.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
NBTI/PBTI-aware wordline voltage control with no boosted supply for stability improvement of half-selected SRAM cells.
Proceedings of the International SoC Design Conference, 2012

CMOS-MEMS capacitive sensors for intra-cranial pressure monitoring: Sensor fabrication & system design.
Proceedings of the International SoC Design Conference, 2012

Recent progress in silicon-based millimeter-wave power amplifier.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2011

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Impacts of NBTI/PBTI on SRAM VMIN and design techniques for SRAM VMIN improvement.
Proceedings of the International SoC Design Conference, 2011

A low-power CAM with efficient power and delay trade-off.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A new match line sensing technique in Content Addressable Memory.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

2010
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 16Kb 10T-SRAM with 4x read-power reduction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Low IR drop and low power parallel CAM design using gated power transistor technique.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008
Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Integrated Circuit Design Research Ranking for Worldwide Universities.
J. Circuits Syst. Comput., 2008

Spicesoft: Automated Tool for Sensitivity Analysis, Performance Analysis, and Inverse Performance Analysis of Digital Circuits.
J. Circuits Syst. Comput., 2008

Body-bootstrapped-buffer circuit for CMOS static power reduction.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A full current-mode sense amplifier for low-power SRAM applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2005
An Ultra Low-power Current-mode Sense Amplifier for Sram Applications.
J. Circuits Syst. Comput., 2005


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