Jiajun Wu
Orcid: 0009-0005-5491-9527Affiliations:
- University of Hong Kong, Department of Electrical and Electronic Engineering, Hong Kong
- Huazhong University of Science and Technology, Wuhan, China (former)
According to our database1,
Jiajun Wu
authored at least 15 papers
between 2019 and 2025.
Collaborative distances:
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Bibliography
2025
TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture.
ACM Trans. Reconfigurable Technol. Syst., 2025
2024
Improving participation equity in dialogic collaborative problem solving: A participatory visual learning analytical approach.
J. Comput. Assist. Learn., August, 2024
DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024
A Case for Low Bitwidth Floating Point Arithmetic on FPGA for Transformer Based DNN Inference.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024
2023
Proceedings of the International Conference on Field Programmable Technology, 2023
Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-Integer Geometric Programming.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023
MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023
2022
In Situ Aging-Aware Error Monitoring Scheme for IMPLY-Based Memristive Computing-in-Memory Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
iTalk-iSee: A participatory visual learning analytical tool for productive peer talk.
Int. J. Comput. Support. Collab. Learn., 2022
Energy-Efficient Intelligent Pulmonary Auscultation for Post COVID-19 Era Wearable Monitoring Enabled by Two-Stage Hybrid Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi-Core Architecture With Transposable Memory and On-Chip Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
A Reconfigurable Area and Energy Efficient Hardware Accelerator of Five High-order Operators for Vision Sensor Based Robot Systems.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
2020
An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
Designing Learning Analytics for Teacher Learning: An Analytics-Supported Teacher Professional Development (ASTPD) Approach.
Proceedings of the 13th International Conference on Computer Supported Collaborative Learning, 2019