Jihyo Kang

Orcid: 0000-0003-1921-8037

According to our database1, Jihyo Kang authored at least 3 papers between 2021 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
IEEE J. Solid State Circuits, 2022

2021
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021


  Loading...