Jinwu Chen

Orcid: 0009-0004-0845-731X

According to our database1, Jinwu Chen authored at least 12 papers between 2011 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs.
IEEE J. Solid State Circuits, March, 2025

14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024
Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

An INT8 Charge-Digital Hybrid Compute-In-Memory Macro With CNN-Friendly Shift-Feed Register Design.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits.
Sci. China Inf. Sci., October, 2023

Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

2022
A Charge-Digital Hybrid Compute-In-Memory Macro with full precision 8-bit Multiply-Accumulation for Edge Computing Devices.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

2011
Automatic Dent-landmark detection in 3-D CBCT dental volumes.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011


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