João Bispo

Orcid: 0000-0002-3017-9449

According to our database1, João Bispo authored at least 62 papers between 2006 and 2024.

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Bibliography

2024
A C Subset for Ergonomic Source-to-Source Analyses and Transformations.
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024

Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study.
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024

A DSL and MLIR Dialect for Streaming and Vectorisation.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023
E-APK: Energy pattern detection in decompiled android applications.
J. Comput. Lang., August, 2023

A DSL-based runtime adaptivity framework for Java.
SoftwareX, July, 2023

Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper).
Proceedings of the 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2023

Enhancing Object Detection in Maritime Environments Using Metadata.
Proceedings of the Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, 2023

Retargeting Applications for Heterogeneous Systems with the Tribble Source-to-Source Framework.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

A CPU-FPGA Holistic Source-To-Source Compilation Approach for Partitioning and Optimizing C/C++ Applications.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
Pegasus: Performance Engineering for Software Applications Targeting HPC Systems.
IEEE Trans. Software Eng., 2022

2021
An Efficient Monte Carlo-Based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System.
IEEE Trans. Emerg. Top. Comput., 2021

Formal verification of Matrix based MATLAB models using interactive theorem proving.
PeerJ Comput. Sci., 2021

A Binary Translation Framework for Automated Hardware Generation.
IEEE Micro, 2021

A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA.
CoRR, 2021

Building Beyond HLS: Graph Analysis and Others.
CoRR, 2021

Multi-language static code analysis on the LARA framework.
Proceedings of the SOAP@PLDI 2021: Proceedings of the 10th ACM SIGPLAN International Workshop on the State Of the Art in Program Analysis, 2021

FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example.
Proceedings of the International Conference on Field-Programmable Technology, 2021

On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators.
Proceedings of the International Conference on Field-Programmable Technology, 2021

2020
Source-to-source compilation targeting OpenMP-based automatic parallelization of C applications.
J. Supercomput., 2020

Clava: C/C++ source-to-source compilation using LARA.
SoftwareX, 2020

Compilation of MATLAB computations to CPU/GPU via C/OpenCL generation.
Concurr. Comput. Pract. Exp., 2020

Overviewing the liveness of refactoring for energy efficiency.
Proceedings of the Programming'20: 4th International Conference on the Art, 2020

Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019
Nonio - modular automatic compiler phase selection and ordering specialization framework for modern compilers.
SoftwareX, 2019

A framework for automatic and parameterizable memoization.
SoftwareX, 2019

The ANTAREX domain specific language for high performance computing.
Microprocess. Microsystems, 2019

The ANTAREX Domain Specific Language for High Performance Computing.
CoRR, 2019


2018
Aspect composition for multiple target languages using LARA.
Comput. Lang. Syst. Struct., 2018

An OpenMP Based Parallelization Compiler for C Applications.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018

Aspect-Driven Mixed-Precision Tuning Targeting GPUs.
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018

AutoPar-Clava: An Automatic Parallelization source-to-source tool for C code applications.
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018

ANTAREX: A DSL-Based Approach to Adaptively Optimizing and Enforcing Extra-Functional Properties in High Performance Computing.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018


2017
A MATLAB subset to C compiler targeting embedded systems.
Softw. Pract. Exp., 2017

The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

LARA as a language-independent aspect-oriented programming approach.
Proceedings of the Symposium on Applied Computing, 2017

Compiler Techniques for Efficient MATLAB to OpenCL Code Generation.
Proceedings of the 5th International Workshop on OpenCL, 2017

Expressing and Applying C++ Code Transformations for the HDF5 API Through a DSL.
Proceedings of the Computer Information Systems and Industrial Management, 2017

2016
SSA-based MATLAB-to-C compilation and optimization.
Proceedings of the 3rd ACM SIGPLAN International Workshop on Libraries, 2016

Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
C and OpenCL generation from MATLAB.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

Techniques for efficient MATLAB-to-C compilation.
Proceedings of the 2nd ACM SIGPLAN International Workshop on Libraries, 2015

Transparent acceleration of program execution using reconfigurable hardware.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Multi-Target C Code Generation from MATLAB.
Proceedings of the ARRAY'14: Proceedings of the 2014 ACM SIGPLAN International Workshop on Libraries, 2014

2013
Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems.
IEEE Trans. Ind. Informatics, 2013

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units.
Int. J. Reconfigurable Comput., 2013

The MATISSE MATLAB compiler.
Proceedings of the 11th IEEE International Conference on Industrial Informatics, 2013

A Risk Diagnosing Methodology Web-Based Platform for Micro, Small and Medium Businesses: Remarks and Enhancements.
Proceedings of the Knowledge Discovery, Knowledge Engineering and Knowledge Management, 2013

A Risk Diagnosing Methodology Web-based Tool for SME's and Start-up Enterprises.
Proceedings of the KDIR/KMIS 2013 - Proceedings of the International Conference on Knowledge Discovery and Information Retrieval and the International Conference on Knowledge Management and Information Sharing, Vilamoura, Algarve, Portugal, 19, 2013

2012
Hardware pipelining of runtime-detected loops.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

2011
From Instruction Traces to Specialized Reconfigurable Arrays.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Techniques for Dynamically Mapping Computations to Coprocessors.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2010
On identifying and optimizing instruction sequences for dynamic compilation.
Proceedings of the International Conference on Field-Programmable Technology, 2010

On Identifying Segments of Traces for Dynamic Compilation.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
A model for emotional contagion based on the emotional contagion scale.
Proceedings of the Affective Computing and Intelligent Interaction, 2009

2008
Regular Expression Matching in Reconfigurable Hardware.
J. Signal Process. Syst., 2008

Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2007
Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Regular expression matching for reconfigurable packet inspection.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006


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