Francesca Palumbo

According to our database1, Francesca Palumbo authored at least 59 papers between 2006 and 2019.

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Bibliography

2019
Editorial: Special Issue on Computing Frontiers.
Signal Processing Systems, 2019

Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing.
Signal Processing Systems, 2019

An integrated hardware/software design methodology for signal processing systems.
J. Syst. Archit., 2019

Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators.
Embedded Systems Letters, 2019

Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding.
IEEE Access, 2019

Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Elicitation of technical requirements in large research projects: the CERBERO approach.
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC.
Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019

CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

NeuPow: artificial neural networks for power and behavioral modeling of arithmetic components in 45nm ASICs technology.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

Optimization and deployment of CNNs at the edge: the ALOHA experience.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

ALOHA: an architectural-aware framework for deep learning at the edge.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

2017
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy.
Signal Processing Systems, 2017

Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs.
J. Syst. Archit., 2017

Hardware design methodology using lightweight dataflow and its integration with low power techniques.
J. Syst. Archit., 2017

Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing.
Embedded Systems Letters, 2017

Exploring the performance of partially reconfigurable point-to-point interconnects.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Adaptive software-augmented hardware reconfiguration with dataflow design automation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Feasibility Study of Real-Time Spiking Neural Network Simulations on a Swarm Intelligence Based Digital Architecture.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Cross-layer design of reconfigurable cyber-physical systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Challenging CPS Trade-off Adaptivity with Coarse-Grained Reconfiguration.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017

2016
Automated Design Flow for Multi-Functional Dataflow-Based Platforms.
Signal Processing Systems, 2016

Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design.
Signal Processing Systems, 2016

On-the-fly adaptivity for process networks over shared-memory platforms.
Microprocess. Microsystems, 2016

MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation.
Microprocess. Microsystems, 2016

Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures.
J. Electrical and Computer Engineering, 2016

Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Demo: Reconfigurable Platform Composer Tool.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Session 2: Architectures for image processing.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Low power design methodology for signal processing systems using lightweight dataflow techniques.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Power and clock gating modelling in coarse grained reconfigurable systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Adaptable AES implementation with power-gating support.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Computing Swarms for Self-Adaptiveness and Self-Organization in Floating-Point Array Processing.
TAAS, 2015

Coarse-grained reconfiguration: dataflow-based power management.
IET Computers & Digital Techniques, 2015

Reconfigurable coprocessors synthesis in the MPEG-RVC domain.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Power modelling for saving strategies in coarse grained reconfigurable systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Exploring custom heterogeneous MPSoCs for real-time neural signal decoding.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

Automated power gating methodology for dataflow-based reconfigurable systems.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms.
J. Real-Time Image Processing, 2014

Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Automatic generation of dataflow-based reconfigurable co-processing units.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

2013
DSE and profiling of multi-context coarse-grained reconfigurable systems.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

Session 2: Tools for DSP algorithm implementation.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

A coarse-grained reconfigurable wavelet denoiser exploiting the Multi-Dataflow Composer tool.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
Multi-purpose systems: A novel dataflow-based generation and mapping strategy.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A nature-inspired adaptive floating-point coprocessing system.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011
The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

Towards self-adaptive networks on chip for massively parallel processors: multilevel quality of service programmability.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations.
IJHPSA, 2010

Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance.
Proceedings of the NOCS 2010, 2010

RVC: A multi-decoder CAL Composer tool.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2008
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs.
Proceedings of the Embedded Computer Systems: Architectures, 2008

A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
A Surface Tension and Coalescence Model for Dynamic Distributed Resources Allocation in Massively Parallel Processors on-Chip.
Proceedings of the Nature Inspired Cooperative Strategies for Optimization (NICSO 2007), 2007

2006
Quantum Correlations in a Generalized Spin Star System.
Open Syst. Inform. Dynam., 2006


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