Jongho Jung
According to our database1,
Jongho Jung
authored at least 3 papers
between 2010 and 2012.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2012
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.
IEEE J. Solid State Circuits, 2012
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2010
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010