Byeongchan Choi
According to our database1,
Byeongchan Choi
authored at least 5 papers
between 2012 and 2020.
Collaborative distances:
Collaborative distances:
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Bibliography
2020
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.
IEEE J. Solid State Circuits, 2020
2019
The isotonic regression approach for an instrumental variable estimation of the potential outcome distributions for compliers.
Comput. Stat. Data Anal., 2019
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2016
Proceedings of the Intelligent Robotics and Applications - 9th International Conference, 2016
2012
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012