Jorge Castro-Godínez

Orcid: 0000-0003-4808-4904

Affiliations:
  • Costa Rica Institute of Technology (TEC), School of Electronics Engineering, Costa Rica
  • Karlsruhe Institute of Technology, Germany (former, PhD 2021)


According to our database1, Jorge Castro-Godínez authored at least 17 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Automatic Generation of Resource and Accuracy Configurable Processing Elements.
ACM Trans. Embed. Comput. Syst., July, 2023

Generic Accuracy Configurable Matrix Multiplication-Addition Accelerator using HLS.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

Cross-Layer Approximations for System-Level Optimizations: Challenges and Opportunities.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

Approximating HW Accelerators through Partial Extractions onto Shared Artificial Neural Networks.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
On the Netlist Gate-level Pruning for Tree-based Machine Learning Accelerators.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

AxRSU: Approximate Radix-4 Squarer Unit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Automated Design of Approximate Accelerators.
PhD thesis, 2021

Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2021

AxLS: A Framework for Approximate Logic Synthesis Based on Netlist Transformations.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

TailoredCore: Generating Application-Specific RISC-V-based Cores.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Multiple approximate instances in neural processing units for energy-efficient circuit synthesis: work-in-progress.
Proceedings of the CASES '21: Proceedings of the 2021 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Virtual Event, October 8, 2021

2020
AUGER: A Tool for Generating Approximate Arithmetic Circuits.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Approximate Acceleration for CNN-based Applications on IoT Edge Devices.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

AxHLS: Design Space Exploration and High-Level Synthesis of Approximate Accelerators using Approximate Functional Units and Analytical Models.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Towards Quality-Driven Approximate Software Generation for Accurate Hardware: Work-in-Progress.
Proceedings of the International Conference on Compilers, 2020

2019
ECAx: Balancing Error Correction Costs in Approximate Accelerators.
ACM Trans. Embed. Comput. Syst., 2019

2018
Compiler-driven error analysis for designing approximate accelerators.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018


  Loading...