Brunno Abreu
Orcid: 0000-0002-0467-0461
According to our database1,
Brunno Abreu
authored at least 23 papers
between 2017 and 2024.
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Bibliography
2024
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024
2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
2022
Energy-Quality Scalable Design Space Exploration of Approximate FFT Hardware Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
C2PAx: Complexity-Aware Constant Parameter Approximation for Energy-Efficient Tree-Based Machine Learning Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers.
IEEE Trans. Computers, 2022
A framework for designing power-efficient inference accelerators in tree-based learning applications.
Eng. Appl. Artif. Intell., 2022
The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures.
Circuits Syst. Signal Process., 2022
Improved Approximate Multipliers for Single-Precision Floating-Point Hardware Design.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 2021 IEEE International Conference on Image Processing, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding.
J. Real Time Image Process., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
2018
Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
2017
Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017