Polychronis Xekalakis

According to our database1, Polychronis Xekalakis authored at least 22 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A Multifaceted Memory Analysis of Java Benchmarks.
Proceedings of the 20th ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes, 2023

Scaling Up Performance of Managed Applications on NUMA Systems.
Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management, 2023

2021
Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2015
Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses.
IEEE Trans. Computers, 2015

2014
Eliminating redundant fragment shader executions on a mobile GPU via hardware memoization.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013
TEAPOT: a toolset for evaluating performance, power and image quality on mobile graphics systems.
Proceedings of the International Conference on Supercomputing, 2013

Parallel frame rendering: Trading responsiveness for energy on a mobile GPU.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Autotuning Skeleton-Driven Optimizations for Transactional Worklist Applications.
IEEE Trans. Parallel Distributed Syst., 2012

Mixed speculative multithreaded execution models.
ACM Trans. Archit. Code Optim., 2012

ASCIB: adaptive selection of cache indexing bits for removing conflict misses.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Boosting mobile GPU performance with a decoupled access/execute fragment processor.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011
Increasing the energy efficiency of TLS systems using intermediate checkpointing.
Proceedings of the 18th International Conference on High Performance Computing, 2011

2010
Mixed speculative multithreaded execution models.
PhD thesis, 2010

Profitability-based power allocation for speculative multithreaded systems.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Toward a more accurate understanding of the limits of the TLS execution paradigm.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

Handling branches in TLS systems with Multi-Path Execution.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2009
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.
Trans. High Perform. Embed. Archit. Compil., 2009

Combining thread level speculation helper threads and runahead execution.
Proceedings of the 23rd international conference on Supercomputing, 2009

2007
Applying Decay to Reduce Dynamic Power in Set-Associative Caches.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore Systems.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2005
A simple mechanism to adapt leakage-control policies to temperature.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

2004
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004


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