Ioannis Papaefstathiou

According to our database1, Ioannis Papaefstathiou
  • authored at least 124 papers between 1999 and 2018.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2018
XSACd - Cross-domain resource sharing & access control for smart environments.
Future Generation Comp. Syst., 2018

The Industrial Internet of Things as an enabler for a Circular Economy Hy-LP: A novel IIoT protocol, evaluated on a wind park's SDN/NFV-enabled 5G industrial network.
Computer Communications, 2018

2017
SCOTRES: Secure Routing for IoT and CPS.
IEEE Internet of Things Journal, 2017

Lightweight & secure industrial IoT communications via the MQ telemetry transport protocol.
Proceedings of the 2017 IEEE Symposium on Computers and Communications, 2017

SecRoute: End-to-end secure communications for wireless ad-hoc networks.
Proceedings of the 2017 IEEE Symposium on Computers and Communications, 2017

An Architecture for the Acceleration of a Hybrid Leaky Integrate and Fire SNN on the Convey HC-2ex FPGA-Based Processor.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

An Open-Source Extendable, Highly-Accurate and Security Aware CPS Simulator.
Proceedings of the 13th International Conference on Distributed Computing in Sensor Systems, 2017

A novel way to efficiently simulate complex full systems incorporating hardware accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Accelerating Intercommunication in Highly Parallel Systems.
TACO, 2016

Software Security, Privacy, and Dependability: Metrics and Measurement.
IEEE Software, 2016

Node.DPWS: Efficient Web Services for the Internet of Things.
IEEE Software, 2016

A survey of lightweight stream ciphers for embedded systems.
Security and Communication Networks, 2016

RtVMF: A Secure Real-Time Vehicle Management Framework.
IEEE Pervasive Computing, 2016

Lightweight authenticated encryption for embedded on-chip systems.
Information Security Journal: A Global Perspective, 2016

Variational Inference Background Subtraction Algorithm for in-Camera Acceleration in Thermal Imagery.
CoRR, 2016

Evaluation of External Memory Access Performance on a High-End FPGA Hybrid Computer.
Computation, 2016

Which IoT Protocol? Comparing Standardized Approaches over a Common M2M Application.
Proceedings of the 2016 IEEE Global Communications Conference, 2016

IoT design course using open-source tools.
Proceedings of the 2016 IEEE Global Engineering Education Conference, 2016

A novel background subtraction scheme for in-camera acceleration in thermal imagery.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Highly efficient reconfigurable parallel graph cuts for embedded vision.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

ECOSCALE: Reconfigurable computing and runtime system for future exascale systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Embedded Systems Security: A Survey of EU Research Efforts.
Security and Communication Networks, 2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Password Hashing Competition - Survey and Benchmark.
IACR Cryptology ePrint Archive, 2015

Node.DPWS: High performance and scalable Web Services for the IoT.
CoRR, 2015

Lightweight Password Hashing Scheme for Embedded Systems.
Proceedings of the Information Security Theory and Practice, 2015

WSACd - A Usable Access Control Framework for Smart Home Devices.
Proceedings of the Information Security Theory and Practice, 2015

COSSIM: A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

Acceleration of Data Streaming Classification using Reconfigurable Technology.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Reconfiguring the Bioinformatics Computational Spectrum: Challenges and Opportunities of FPGA-Based Bioinformatics Acceleration Platforms.
IEEE Design & Test, 2014

Policy-Based Access Control for Body Sensor Networks.
Proceedings of the Information Security Theory and Practice. Securing the Internet of Things, 2014

A Reasoning System for Composition Verification and Security Validation.
Proceedings of the 6th International Conference on New Technologies, Mobility and Security, 2014

Evaluation of RPL with a transmission count-efficient and trust-aware routing metric.
Proceedings of the IEEE International Conference on Communications, 2014

HPC-gSpan: An FPGA-based parallel system for frequent subgraph mining.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Policy-based access control for DPWS-enabled ubiquitous devices.
Proceedings of the 2014 IEEE Emerging Technology and Factory Automation, 2014

A novel embedded system for vision tracking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Effective Reconfigurable Design: The FASTER Approach.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

ModConTR: A modular and configurable trust and reputation-based system for secure routing in ad-hoc networks.
Proceedings of the 11th IEEE/ACS International Conference on Computer Systems and Applications, 2014

2013
Evaluating routing metric composition approaches for QoS differentiation in low power and lossy networks.
Wireless Networks, 2013

A novel low-power embedded object recognition system working at multi-frames per second.
ACM Trans. Embedded Comput. Syst., 2013

Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems.
TACO, 2013

HC-CART: A parallel system implementation of data mining classification and regression tree (CART) algorithm on a multi-FPGA system.
TACO, 2013

HEAP: A Highly Efficient Adaptive multi-Processor framework.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

IPv6 security for low power and lossy networks.
Proceedings of the IFIP Wireless Days, 2013

A lightweight anonymity & location privacy service.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2013

Fast, FPGA-based Rainbow Table creation for attacking encrypted mobile communications.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Parallelizing bioinformatics and security applications on a low-cost multi-core system.
Proceedings of the ACS International Conference on Computer Systems and Applications, 2013

2012
Fast and power-efficient hardware implementation of a routing scheme for WSNs.
Proceedings of the 2012 IEEE Wireless Communications and Networking Conference, 2012

Using hardware-based forward error correction to reduce the overall energy consumption of WSNs.
Proceedings of the 2012 IEEE Wireless Communications and Networking Conference, 2012

ROTA: An Archipelago-Wide Area Network for High Speed Communication to Ships.
Proceedings of the 16th Panhellenic Conference on Informatics, PCI 2012, 2012

Breaking the GSM A5/1 cryptography algorithm with rainbow tables and high-end FPGAS.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A novel low-power embedded object recognition system working at multi-frames per second (Extended abstract).
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

HEAP: A Highly Efficient Adaptive Multi-processor Framework.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

An FPGA-based parallel processor for Black-Scholes option pricing using finite differences schemes.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
RESENSE: An Innovative, Reconfigurable, Powerful and Energy Efficient WSN Node.
Proceedings of IEEE International Conference on Communications, 2011

FPGA power consumption measurements and estimations under different implementation parameters.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Novel and Highly Efficient Reconfigurable Implementation of Data Mining Classification Tree.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic and on a GPU.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Parallel accelerators for GlimmerHMM bioinformatics algorithm.
Proceedings of the Design, Automation and Test in Europe, 2011

Reconfigurable Computing IP Cores for Multiple Sequence Alignment.
Proceedings of the BIOINFORMATICS 2011, 2011

2010
Titan-R: A Multigigabit Reconfigurable Combined Compression/Decompression Unit.
TRETS, 2010

An Open-Source Scaled Automobile Platform for Fault-Tolerant Electronic Stability Control.
IEEE Trans. Instrumentation and Measurement, 2010

Development and implementation of a Network Processor Architecture in reconfigurable logic (FPGA).
Proceedings of the 8th Workshop on Intelligent Solutions in Embedded Systems, 2010

Using Reconfigurable Hardware Devices in WSNs for Reducing the Energy Consumption of Routing and Security Tasks.
Proceedings of the Global Communications Conference, 2010

Implementing Rainbow Tables in High-End FPGAs for Super-Fast Password Cracking.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Fast and Efficient FPGA-Based Feature Detection Employing the SURF Algorithm.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

2009
Accelerating Emulation and Providing Full Chip Observability and Controllability.
IEEE Design & Test of Computers, 2009

High-speed FPGA-based implementations of a Genetic Algorithm.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Design and Implementation of an UWB Digital Transmitter Based on the Multiband OFDM Physical Layer Proposal.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A self-reconfiguring architecture supporting multiple objective functions in genetic algorithms.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A FPGA based coprocessor for gene finding using Interpolated Markov Model (IMM).
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Implementation of a genetic algorithm on a virtex-ii pro FPGA.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Securing wireless sensor networks towards a trusted "Internet of Things".
Proceedings of the Towards the Future Internet - A European Research Perspective, 2009

High-End Reconfigurable Systems for Fast Windows' Password Cracking.
Proceedings of the FCCM 2009, 2009

Design and implementation of a database filter for BLAST acceleration.
Proceedings of the Design, Automation and Test in Europe, 2009

Heavily Reducing WSNs' Energy Consumption by Employing Hardware-Based Compression.
Proceedings of the Ad-Hoc, Mobile and Wireless Networks, 8th International Conference, 2009

2008
Building an FoC Using Large, Buffered Crossbar Cores.
IEEE Design & Test of Computers, 2008

Power Consumption Estimations vs Measurements for FPGA-Based Security Cores.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

A Multi Gigabit FPGA-Based 5-tuple Classification System.
Proceedings of IEEE International Conference on Communications, 2008

Accelerating hardware simulation: Testbench code emulation.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Titan-R: A Reconfigurable Hardware Implementation of a High-Speed Compressor.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

A Memory-Efficient FPGA-based Classification Engine.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

MPLEM: An 80-processor FPGA Based Multiprocessor System.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2007
Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units.
Microprocessors and Microsystems, 2007

Queue Management in Network Processors
CoRR, 2007

A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Hardware Implementation of 2-Opt Local Search Algorithm for the Traveling Salesman Problem.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

An Embedded Networking SoC for purely Ethernet MANs/WANs.
Proceedings of the 12th IEEE Symposium on Computers and Communications (ISCC 2007), 2007

Memory-Efficient 5D Packet Classification At 40 Gbps.
Proceedings of the INFOCOM 2007. 26th IEEE International Conference on Computer Communications, 2007

A buffered crossbar-based chip interconnection framework supporting quality of service.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

An efficient FPGA-based implementation of Pollard's (ρ - 1) factorization algorithm.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Efficient testbench code synthesis for a hardware emulator system.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks.
Proceedings of IEEE International Conference on Communications, 2006

A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005
A Memory Efficient, 100 Gb/sec MAC Classification Engine.
Proceedings of the 30th Annual IEEE Conference on Local Computer Networks (LCN 2005), 2005

Queue Management in Network Processors.
Proceedings of the 2005 Design, 2005

A Low-Power Processor Architecture Optimized forWireless Devices.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
PRO3: A Hybrid NPU Architecture.
IEEE Micro, 2004

Guest Editors' Introduction: Network Processors for Future High-End Systems and Applications.
IEEE Micro, 2004

Design-space exploration of the most widely used cryptography algorithms.
Microprocessors and Microsystems, 2004

An FPGA-based queue management system for high speed networking devices.
Microprocessors and Microsystems, 2004

Low Level Hardware Compression for Multi-gigabit Networks.
Journal of Circuits, Systems, and Computers, 2004

Packet Processing acceleration with a 3-stage programmable pipeline engine.
IEEE Communications Letters, 2004

Titan II: An IPcomp Processor for 10-Gbps Networks.
IEEE Design & Test of Computers, 2004

Variable packet size buffered crossbar (CICQ) switches.
Proceedings of IEEE International Conference on Communications, 2004

Software Processing Performance in Network Processors.
Proceedings of the 2004 Design, 2004

2003
Titan II : An IPComp Processor for 10Gbit/sec networks.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

An innovative scheduling scheme for high-speed network processors.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Active flow identifiers for scalable, QoS scheduling in 10-Gbps network processors.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Design-space exploration of a cryptography algorithm.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Performance against cost trade-offs for hardware compression in 10 Gigabit networks.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

An Innovative Resource Management Scheme for Multi-gigabit Networking Systems.
Proceedings of the High Speed Networks and Multimedia Communications, 2003

A fully-programmable memory management system optimizing queue handling at multi-gigabit rates.
Proceedings of the 40th Design Automation Conference, 2003

GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Read, use, simulate, experiment and build: an integrated approach for teaching computer architecture.
Proceedings of the 2002 workshop on Computer architecture education, 2002

2000
Measurement Based Connection Admission Control Algorithm for ATM Networks that Use Low Level Compression.
Proceedings of the Telecommunications and IT Convergence Towards Service E-volution, 2000

1999
Accelerating ATM: on-line compression of ATM streams.
Proceedings of the IEEE International Performance Computing and Communications Conference, 1999

Compressing ATM Streams On-Line.
Proceedings of the Data Compression Conference, 1999


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