Alberto Scionti

According to our database1, Alberto Scionti authored at least 31 papers between 2008 and 2019.

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Bibliography

2019
Chip-to-Cloud: an Autonomous and Energy Efficient Platform for Smart Vision Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019


Smart Scheduling Strategy for Lightweight Virtualized Resources Towards Green Computing.
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2019

Low Power Wireless Networks for Extremely Critical Environments.
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2019

Unmanned Aerial Vehicle for the Inspection of Environmental Emissions.
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2019

2018
Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud.
Sensors, 2018

Enabling Massive Multi-Threading with Fast Hashing.
Computer Architecture Letters, 2018

Towards Energy Efficient Orchestration of Cloud Computing Infrastructure.
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2018

2017
Adaptive Resource Allocation for Load Balancing in Cloud.
Proceedings of the Cloud Computing - Principles, Systems and Applications, Second Edition, 2017

Efficient Data-Driven Task Allocation for Future Many-Cluster On-chip Systems.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

A Scalable and Low-Power FPGA-Aware Network-on-Chip Architecture.
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2017

Let's Go: a Data-Driven Multi-Threading Support.
Proceedings of the Computing Frontiers Conference, 2017

2016
SIERRA - Simulation environment for memory redundancy algorithms.
Simulation Modelling Practice and Theory, 2016

Software defined Network-on-Chip for scalable CMPs.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

OPERA: A Low Power Approach to the Next Generation Cloud Infrastructures.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

DemoGRAPE: Managing Scientific Applications in a Cloud-Federated Environment.
Proceedings of the 10th International Conference on Complex, 2016

Workload Management for Power Efficiency in Heterogeneous Data Centers.
Proceedings of the 10th International Conference on Complex, 2016

Low Power Computing and Communication System for Critical Environments.
Proceedings of the Advances on P2P, 2016

2015
A scalable thread scheduling co-processor based on data-flow principles.
Future Generation Comp. Syst., 2015

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Enhancing an x86_64 multi-core architecture with data-flow execution support.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2012
FPGA-Based Remote-Code Integrity Verification of Programs in Distributed Embedded Systems.
IEEE Trans. Systems, Man, and Cybernetics, Part C, 2012

Simulating the future kilo-x86-64 core processors and their infrastructure.
Proceedings of the 2012 Spring Simulation Multiconference, 2012

2011
Increasing pattern recognition accuracy for chemical sensing by evolutionary based drift compensation.
Pattern Recognition Letters, 2011

Genetic Defect Based March Test Generation for SRAM.
Proceedings of the Applications of Evolutionary Computation, 2011

2010
Towards drift correction in chemical sensors using an evolutionary strategy.
Proceedings of the Genetic and Evolutionary Computation Conference, 2010

Exploiting Evolution for an Adaptive Drift-Robust Classifier in Chemical Sensing.
Proceedings of the Applications of Evolutionary Computation, 2010

2009
A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Automating defects simulation and fault modeling for SRAMs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Functional testing approaches for "BIFST-able" tlm_fifo.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Influence of Parasitic Capacitance Variations on 65 nm and 32 nm Predictive Technology Model SRAM Core-Cells.
Proceedings of the 17th IEEE Asian Test Symposium, 2008


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