Josep Llosa

According to our database, Josep Llosa authored at least 51 papers between 1994 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

ECCPA: Calculation of classical and quantum cross sections for elastic collisions of charged particles with atoms.

Francesc Salvat, Josep Llosa, Antonio M. Lallena, Julio Almansa

Comput. Phys. Commun., 2022

Lightning Talks of EduHPC 2022.

Apan Qasem, Hartwig Anzt, Eduard Ayguadé, Katharine Cahill, Ramon Canal, Jany Chan, Eric Fosler-Lussier, Fritz Göbel, Arpan Jain, Marcel Koch, Mateusz Kuzak, Josep Llosa, Raghu Machiraju, Xavier Martorell, Pratik Nayak, Shameema Oottikkal, Marcin Ostasz, Dhabaleswar K. Panda, Dirk Pleiter, Rajiv Ramnath, Maria-Ribera Sancho, Alessio Sclocco, Aamir Shafi, Hanno Spreeuw, Hari Subramoni, Karen Tomko

Proceedings of the IEEE/ACM International Workshop on Education for High Performance Computing, 2022

2010

CSMT: Simultaneous Multithreading for Clustered VLIW Processors.

Manoj Gupta, Fermín Sánchez, Josep Llosa

IEEE Trans. Computers, 2010

A low cost split-issue technique to improve performance of SMT clustered VLIW processors.

Manoj Gupta, Fermín Sánchez, Josep Llosa

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2009

Thread Merging Schemes for Multithreaded Clustered VLIW Processors.

Manoj Gupta, Fermín Sánchez, Josep Llosa

Proceedings of the ICPP 2009, 2009

Hybrid multithreading for VLIW processors.

Manoj Gupta, Fermín Sánchez, Josep Llosa

Proceedings of the 2009 International Conference on Compilers, 2009

2008

Power-efficient VLIW design using clustering and widening.

Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero

Int. J. Embed. Syst., 2008

2007

Cluster-level simultaneous multithreading for VLIW processors.

Manoj Gupta, Fermín Sánchez, Josep Llosa

Proceedings of the 25th International Conference on Computer Design, 2007

Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration.

Kolin Paul, Joël Porquet, Josep Llosa

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Merge Logic for Clustered Multithreaded VLIW Processors.

Manoj Gupta, Fermín Sánchez, Josep Llosa

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2005

An accurate cost model for guiding data locality transformations.

Xavier Vera, Jaume Abella, Josep Llosa, Antonio González

ACM Trans. Program. Lang. Syst., 2005

2004

Register Constrained Modulo Scheduling.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

IEEE Trans. Parallel Distributed Syst., 2004

A fast and accurate framework to analyze and optimize cache memory behavior.

Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González

ACM Trans. Program. Lang. Syst., 2004

A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors.

Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero

SIGARCH Comput. Archit. News, 2004

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Int. J. Parallel Program., 2004

High-performance and low-power VLIW cores for numerical computations.

Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero

Int. J. High Perform. Comput. Netw., 2004

Future ILP processors.

Adrián Cristal, Josep Llosa, Mateo Valero, Daniel Ortega

Int. J. High Perform. Comput. Netw., 2004

Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units.

Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero

Proceedings of the Computer Systems: Architectures, 2004

Out-of-Order Commit Processors.

Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero

Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

2003

A Case for Resource-conscious Out-of-order Processors.

Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero

IEEE Comput. Archit. Lett., 2003

Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes.

Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero

Proceedings of the High Performance Computing, 5th International Symposium, 2003

Kilo-instruction Processors.

Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero

Proceedings of the High Performance Computing, 5th International Symposium, 2003

Hierarchical Clustered Register File Organization for VLIW Processors.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Optimizing Program Locality Through CMEs and GAs.

Xavier Vera, Jaume Abella, Antonio González, Josep Llosa

Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002

Reduced code size modulo scheduling in the absence of hardware support.

Josep Llosa, Stefan M. Freudenberger

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Near-Optimal Padding for Removing Conflict Misses.

Xavier Vera, Josep Llosa, Antonio González

Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002

A comparative study of modulo scheduling techniques.

Josep M. Codina, Josep Llosa, Antonio González

Proceedings of the 16th international conference on Supercomputing, 2002

Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms.

Jaume Abella, Antonio González, Josep Llosa, Xavier Vera

Proceedings of the 31st International Conference on Parallel Processing Workshops (ICPP 2002 Workshops), 2002

2001

Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures.

David López, Josep Llosa, Mateo Valero, Eduard Ayguadé

IEEE Trans. Computers, 2001

Lifetime-Sensitive Modulo Scheduling in a Production Environment.

Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt

IEEE Trans. Computers, 2001

Modulo scheduling with integrated register spilling for clustered VLIW architectures.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

<i>MIRS</i>: Modulo Scheduling with Integrated Register Spilling.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Proceedings of the Languages and Compilers for Parallel Computing, 2001

2000

Optimizing cache miss equations polyhedra.

Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa

SIGARCH Comput. Archit. News, 2000

Improved spill code generation for software pipelined loops.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Proceedings of the 2000 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2000

Two-level hierarchical register file organization for VLIW processors.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

An efficient solver for Cache Miss Equations.

Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa

Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000

A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note).

Xavier Vera, Josep Llosa, Antonio González, Nerina Bermudo

Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999

Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures.

David López, Josep Llosa, Eduard Ayguadé, Mateo Valero

Proceedings of the International Conference on Parallel Processing 1999, 1999

Distributed Modulo Scheduling.

Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham

Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998

Modulo Scheduling with Reduced Register Pressure.

Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González

IEEE Trans. Computers, 1998

Quantitative Evaluation of Register Pressure on Software Pipelined Loops.

Josep Llosa, Eduard Ayguadé, Mateo Valero

Int. J. Parallel Program., 1998

Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures.

David López, Josep Llosa, Mateo Valero, Eduard Ayguadé

Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

Partitioned Schedules for Clustered VLIW Architectures.

Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham

Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

Resource Widening Versus Replication: Limits and Performance-cost Trade-off.

David López, Josep Llosa, Mateo Valero, Eduard Ayguadé

Proceedings of the 12th international conference on Supercomputing, 1998

1997

Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs.

David López, Mateo Valero, Josep Llosa, Eduard Ayguadé

Proceedings of the 11th international conference on Supercomputing, 1997

Allocating Lifetimes to Queues in Software Pipelined Architectures.

Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham

Proceedings of the Euro-Par '97 Parallel Processing, 1997

1996

Heuristics for Register-Constrained Software Pipelining.

Josep Llosa, Mateo Valero, Eduard Ayguadé

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Swing module scheduling: a lifetime-sensitive approach.

Josep Llosa, Antonio González, Eduard Ayguadé, Mateo Valero

Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1995

Hypernode reduction modulo scheduling.

Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Non-Consistent Dual Register Files to Reduce Register Pressure.

Josep Llosa, Mateo Valero, Eduard Ayguadé

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

1994

Using Sacks to Organize Registers in VLIW Machines.

Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé

Proceedings of the Parallel Processing: CONPAR 94, 1994