Joseph Natonio

According to our database, Joseph Natonio authored at least 3 papers between 2000 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2011

A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology.

Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William R. Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2005

A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications.

Ram Kelkar, Dave Flye, Anjali Malladi, Joseph Natonio, Chri Scoville, Ken Short, Pradeep Thiagarajan

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

2000

Methodology for I/O cell placement and checking in ASIC designs using area-array power grid.

Patrick H. Buffet, Joseph Natonio, Robert A. Proctor, Yu H. Sun, Gulsun Yasar

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000