Mounir Meghelli

According to our database1, Mounir Meghelli authored at least 48 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits, 2023

2022


2020
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits, 2020

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS.
IEEE J. Solid State Circuits, 2020

2019
Toward Optical Networks using Rapid Amplified Multi-Wavelength Photonic Switches.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019


A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2018

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018

FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

F5: Advanced optical communication: From devices, circuits, and architectures to algorithms.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Session 6 overview: Ultra-high-speed wireline: Wireline subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2017

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2017

6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Internet of the Body and Cognitive Hypervisor.
Proceedings of the Second IEEE/ACM International Conference on Connected Health: Applications, 2017

2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016


3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks.
IEEE J. Solid State Circuits, 2015

A 25 Gb/s burst-mode receiver for low latency photonic switch networks.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2014

2013
A linearized voltage-controlled oscillator for dual-path phase-locked loops.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2012

2008
Introduction to the Special Section on the 2008 Compound Semiconductor Integrated Circuit Symposium (CSICS'08).
IEEE J. Solid State Circuits, 2008

2006
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology.
IEEE J. Solid State Circuits, 2006

Phase and amplitude pre-emphasis techniques for low-power serial links.
IEEE J. Solid State Circuits, 2006


2005
A 43-Gb/s full-rate clock transmitter in 0.18-μm SiGe BiCMOS technology.
IEEE J. Solid State Circuits, 2005

A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS.
IEEE J. Solid State Circuits, 2005

2004
132-Gb/s 4: 1 multiplexer in 0.13-μm SiGe-bipolar technology.
IEEE J. Solid State Circuits, 2004

2003
A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems.
IEEE J. Solid State Circuits, 2003

SiGe BiCMOS integrated circuits for high-speed serial communication links.
IBM J. Res. Dev., 2003

45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence].
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems.
IEEE J. Solid State Circuits, 2002

40-Gb/s circuits built from a 120-GHz f<sub>T</sub> SiGe technology.
IEEE J. Solid State Circuits, 2002

2000
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits.
Proc. IEEE, 2000

SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems.
IEEE J. Solid State Circuits, 2000

1998
High power and high speed InP DHBT driver IC's for laser modulation.
IEEE J. Solid State Circuits, 1998

InP DHBT technology and design methodology for high-bit-rate optical communications circuits.
IEEE J. Solid State Circuits, 1998

Very high speed integrated circuits for optical communication.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


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