Serkan Ozdemir

Orcid: 0000-0002-8635-3311

According to our database1, Serkan Ozdemir authored at least 11 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A systematic literature review on lake water level prediction models.
Environ. Model. Softw., May, 2023

2012
Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2010
Quantifying and coping with parametric variations in 3D-stacked microarchitectures.
Proceedings of the 47th Design Automation Conference, 2010

2009
Selective wordline voltage boosting for caches to manage yield under process variations.
Proceedings of the 46th Design Automation Conference, 2009

2008
Microarchitectures for Managing Chip Revenues under Process Variations.
IEEE Comput. Archit. Lett., 2008

Evaluating the effects of cache redundancy on profit.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

2007
Thermal Management of On-Chip Caches Through Power Density Minimization.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Variable latency caches for nanoscale processor.
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007

Evaluating voltage islands in CMPs under process variations.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Yield-Aware Cache Architectures.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Power density minimization for highly-associative caches in embedded processors.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006


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