Jun-Shen Wu
Orcid: 0000-0003-3816-3350
According to our database1,
Jun-Shen Wu
authored at least 7 papers
between 2019 and 2023.
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Bibliography
2023
SG-Float: Achieving Memory Access and Computing Power Reduction Using Self-Gating Float in CNNs.
ACM Trans. Embed. Comput. Syst., November, 2023
FM-P2L: An Algorithm Hardware Co-design of Fixed-Point MSBs with Power-of-2 LSBs in CNN Accelerators.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
2022
ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
2021
Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN).
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019