Chih-Cheng Hsieh

According to our database1, Chih-Cheng Hsieh authored at least 72 papers between 1997 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020

MARS: Multi-macro Architecture SRAM CIM-Based Accelerator with Co-designed Compressed Neural Networks.
CoRR, 2020

15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator.
IEEE J. Solid State Circuits, 2019

An ULV PWM CMOS Imager With Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting.
IEEE J. Solid State Circuits, 2019

A Calibration-Free 13-Bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded Op-Amps.
IEEE J. Solid State Circuits, 2019

A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors.
IEEE J. Solid State Circuits, 2019

Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Current-Mode Differential Sensing CMOS Imager for Optical Linear Encoder.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 40MS/s 12-bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A CMOS Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation and Phase Shifting Readout Technique.
IEEE J. Solid State Circuits, 2018

A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization.
IEEE J. Solid State Circuits, 2018

A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC.
IEEE J. Solid State Circuits, 2018

A 12-bit 150-MS/s Sub-Radix-3 SAR ADC With Switching Miller Capacitance Reduction.
IEEE J. Solid State Circuits, 2018

A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-Amps.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Hybrid Analog-to-Digital Conversion Algorithm With Sub-Radix and Multiple Quantization Thresholds.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A CMOS time of flight (TOF) depth image sensor with in-pixel background cancellation and sensitivity improvement using phase shifting readout technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 137 dB Dynamic Range and 0.32 V Self-Powered CMOS Imager With Energy Harvesting Pixels.
IEEE J. Solid State Circuits, 2016

A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS.
IEEE J. Solid State Circuits, 2016

A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 0.4V 1.94fJ/conversion-step 10b 750kS/s SAR ADC with input-range-adaptive switching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

A time delay multiple integration linear CMOS image sensor for multispectral satellite telemetry.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

An integrated CMOS optical sensing chip for multiple bio-signal detections.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 0.4V self-powered CMOS imager with 140dB dynamic range and energy harvesting.
Proceedings of the Symposium on VLSI Circuits, 2015

An in-pixel equalizer with kTC noise cancellation and FPN reduction for time-of-flight CMOS image sensor.
Proceedings of the VLSI Design, Automation and Test, 2015

An 8-bit column-shared SAR ADC for CMOS image sensor applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 132dB DR readout IC with pulse width modulation for IR focal plane arrays.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia.
IEEE Trans. Biomed. Circuits Syst., 2014

A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

A dual-mode CMOS image sensor for optical wireless communication.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

A signal acquisition and processing chip with built-in cluster for chemiresistive gas sensor array.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
2.4-GHz 10-Mb/s BFSK Embedded Transmitter With a Stacked-LC DCO for Wireless Testing Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A 3 Megapixel 100 Fps 2.8 µm Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers.
IEEE J. Solid State Circuits, 2013

A 0.5 V PWM CMOS Imager With 82 dB Dynamic Range and 0.055% Fixed-Pattern-Noise.
IEEE J. Solid State Circuits, 2013

A 1V 14kfps smart CMOS imager with tracking and edge-detection modes for biomedical monitoring.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Exploration of Second-Order Effects in High-Performance Continuous-Time ΣΔ Modulators Using Discrete-Time Models.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noise.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Low-Power Electronic Nose Signal-Processing Chip for a Portable Artificial Olfaction System.
IEEE Trans. Biomed. Circuits Syst., 2011

A 0.6V CMOS Image Sensor with in-pixel biphasic current driver for biomedical application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Live demonstration: The prototype of real-time image pre-processing system for satellites' remote sensing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A new CMOS image sensor readout structure for 3D integrated imagers.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A 0.8V 64×64 CMOS imager with integrated sense-and-stimulus pixel for artificial retina applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A High Performance Linear Current Mode Image Sensor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

1997
Focal-plane-arrays and CMOS readout techniques of infrared imaging systems.
IEEE Trans. Circuits Syst. Video Technol., 1997


  Loading...