Chih-Cheng Hsieh
Orcid: 0000-0003-4070-5059
According to our database1,
Chih-Cheng Hsieh
authored at least 109 papers
between 1997 and 2024.
Collaborative distances:
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Bibliography
2024
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices.
IEEE J. Solid State Circuits, January, 2024
A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips.
IEEE J. Solid State Circuits, January, 2024
A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme.
IEEE J. Solid State Circuits, January, 2024
34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification.
IEEE J. Solid State Circuits, November, 2023
A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision.
IEEE J. Solid State Circuits, October, 2023
A 12-ENOB Second-Order Noise-Shaping SAR ADC With PVT-Insensitive Voltage- Time-Voltage Converter.
IEEE J. Solid State Circuits, October, 2023
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.
IEEE J. Solid State Circuits, March, 2023
8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices.
IEEE J. Solid State Circuits, 2023
A -20°C~+107°C 52mk-NETD Reference-cell-free 15-bits ROIC for 80×60 Micro-bolometer Thermal Imager.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.
IEEE J. Solid State Circuits, 2022
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips.
IEEE J. Solid State Circuits, 2021
A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction.
IEEE J. Solid State Circuits, 2021
A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel.
IEEE J. Solid State Circuits, 2021
A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Integer Quadratic Integrate-and-Fire (IQIF): A Neuron Model for Digital Neuromorphic Systems.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
A Bio-Inspired Motion Detection Circuit Model for the Computation of Optical Flow: The Spatial-Temporal Filtering Reichardt Model.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020
A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020
MARS: Multi-macro Architecture SRAM CIM-Based Accelerator with Co-designed Compressed Neural Networks.
CoRR, 2020
15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A Monolithic Optical Encoder using CMOS Image Sensor with Background Light Cancellation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
IEEE J. Solid State Circuits, 2019
An ULV PWM CMOS Imager With Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting.
IEEE J. Solid State Circuits, 2019
A Calibration-Free 13-Bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded Op-Amps.
IEEE J. Solid State Circuits, 2019
A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors.
IEEE J. Solid State Circuits, 2019
Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 40MS/s 12-bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A CMOS Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation and Phase Shifting Readout Technique.
IEEE J. Solid State Circuits, 2018
A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization.
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-Amps.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Hybrid Analog-to-Digital Conversion Algorithm With Sub-Radix and Multiple Quantization Thresholds.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A CMOS imaging platform using single photon avalanche diode array in standard technology.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017
A CMOS time of flight (TOF) depth image sensor with in-pixel background cancellation and sensitivity improvement using phase shifting readout technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 137 dB Dynamic Range and 0.32 V Self-Powered CMOS Imager With Energy Harvesting Pixels.
IEEE J. Solid State Circuits, 2016
A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A 0.4V 1.94fJ/conversion-step 10b 750kS/s SAR ADC with input-range-adaptive switching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016
Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
A time delay multiple integration linear CMOS image sensor for multispectral satellite telemetry.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the Symposium on VLSI Circuits, 2015
An in-pixel equalizer with kTC noise cancellation and FPN reduction for time-of-flight CMOS image sensor.
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia.
IEEE Trans. Biomed. Circuits Syst., 2014
A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
A signal acquisition and processing chip with built-in cluster for chemiresistive gas sensor array.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
2.4-GHz 10-Mb/s BFSK Embedded Transmitter With a Stacked-LC DCO for Wireless Testing Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013
A 3 Megapixel 100 Fps 2.8 µm Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers.
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
A 1V 14kfps smart CMOS imager with tracking and edge-detection modes for biomedical monitoring.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Exploration of Second-Order Effects in High-Performance Continuous-Time ΣΔ Modulators Using Discrete-Time Models.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noise.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
A Low-Power Electronic Nose Signal-Processing Chip for a Portable Artificial Olfaction System.
IEEE Trans. Biomed. Circuits Syst., 2011
A 0.6V CMOS Image Sensor with in-pixel biphasic current driver for biomedical application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Live demonstration: The prototype of real-time image pre-processing system for satellites' remote sensing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
A 0.8V 64×64 CMOS imager with integrated sense-and-stimulus pixel for artificial retina applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
A new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
1998
High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA.
IEEE J. Solid State Circuits, 1998
1997
IEEE Trans. Circuits Syst. Video Technol., 1997
IEEE J. Solid State Circuits, 1997